malidp_write32_mask
malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl);
malidp_write32_mask(c->reg, BLK_CONTROL, BS_CTRL_EN, 0);
malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0);
malidp_write32_mask(reg, BLK_CONTROL, ctrl_mask, ctrl);
malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl);
malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0);
malidp_write32_mask(reg, BLK_STATUS, status, 0);
malidp_write32_mask(reg, BLK_STATUS, restore, 0);
malidp_write32_mask(d71->gcu_addr, BLK_STATUS,
malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK,
malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, ENABLED_GCU_IRQS, 0);
malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode);
malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_CONNECT_MODE);
malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE);
malidp_write32_mask(d71->pipes[i]->lpu_addr, LPU_TBU_CONTROL,
malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_DISCONNECT_MODE);
malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE);
malidp_write32_mask(reg, BLK_STATUS, restore, 0);
malidp_write32_mask(reg, LPU_TBU_STATUS, restore, 0);