malidp_write32
malidp_write32(base, offset, v | tmp);
malidp_write32(base, offset + i * 4, values[i]);
malidp_write32(reg, BLK_INPUT_ID0 + index * 4,
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
malidp_write32(reg, IPS_DEPTH, st->color_depth);
malidp_write32(reg, BS_ACTIVESIZE, HV_SIZE(hactive, vactive));
malidp_write32(reg, BS_HINTERVALS, BS_H_INTVALS(hfront_porch,
malidp_write32(reg, BS_VINTERVALS, BS_V_INTVALS(vfront_porch,
malidp_write32(reg, BS_SYNC, value);
malidp_write32(reg, BS_PROG_LINE, D71_DEFAULT_PREPRETCH_LINE - 1);
malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
malidp_write32(reg, BLK_CONTROL, value);
malidp_write32(reg, BLK_P1_STRIDE, fb->pitches[1] * block_h);
malidp_write32(reg, BLK_P0_STRIDE, fb->pitches[0] * block_h);
malidp_write32(reg, LAYER_FMT, kfb->format_caps->hw_id);
malidp_write32(reg, AD_CONTROL, to_ad_ctrl(fb->modifier));
malidp_write32(reg, LAYER_AD_H_CROP, HV_CROP(st->afbc_crop_l,
malidp_write32(reg, LAYER_AD_V_CROP, HV_CROP(st->afbc_crop_t,
malidp_write32(reg, BLK_P1_PTR_LOW, lower_32_bits(addr));
malidp_write32(reg, BLK_P1_PTR_HIGH, upper_32_bits(addr));
malidp_write32(reg, LAYER_R_CONTROL, upsampling);
malidp_write32(reg, BLK_IN_SIZE, HV_SIZE(st->hsize, st->vsize));
malidp_write32(reg, LAYER_PALPHA, D71_PALPHA_DEF_MAP);
malidp_write32(reg, BLK_IN_SIZE, HV_SIZE(st->hsize, st->vsize));
malidp_write32(reg, BLK_INPUT_ID0, to_d71_input_id(state, 0));
malidp_write32(c->reg, BLK_INPUT_ID0, 0);
malidp_write32(reg, BLK_CONTROL, 0);
malidp_write32(reg, BLK_INPUT_ID0 + (i << 2), 0);
malidp_write32(reg, CU_INPUT0_CONTROL +
malidp_write32(id_reg, BLK_INPUT_ID0, input_hw_id);
malidp_write32(cfg_reg, CU_INPUT0_SIZE,
malidp_write32(cfg_reg, CU_INPUT0_OFFSET,
malidp_write32(cfg_reg, CU_INPUT0_CONTROL, ctrl);
malidp_write32(id_reg, BLK_INPUT_ID0, 0);
malidp_write32(cfg_reg, CU_INPUT0_CONTROL, 0);
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
malidp_write32(reg, SC_COEFFTAB, val);
malidp_write32(reg, BLK_IN_SIZE, HV_SIZE(st->hsize_in, st->vsize_in));
malidp_write32(reg, SC_OUT_SIZE, HV_SIZE(st->hsize_out, st->vsize_out));
malidp_write32(reg, SC_H_CROP, HV_CROP(st->left_crop, st->right_crop));
malidp_write32(reg, SC_H_INIT_PH, init_ph);
malidp_write32(reg, SC_H_DELTA_PH, delta_ph);
malidp_write32(reg, SC_V_INIT_PH, init_ph);
malidp_write32(reg, SC_V_DELTA_PH, delta_ph);
malidp_write32(reg, BLK_CONTROL, ctrl);
malidp_write32(reg, BLK_INPUT_ID0, to_d71_input_id(state, 0));
malidp_write32(c->reg, BLK_CONTROL, 0);
malidp_write32(reg, BLK_INPUT_ID0, to_d71_input_id(state, 0));
malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize));
malidp_write32(reg, SP_OVERLAP_SIZE, st->overlap & 0x1FFF);
malidp_write32(reg, BLK_CONTROL, BLK_CTRL_EN);
malidp_write32(reg, MG_INPUT_ID0 + index * 4,
malidp_write32(reg, MG_SIZE, HV_SIZE(st->hsize_merged,
malidp_write32(reg, BLK_CONTROL, BLK_CTRL_EN);
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
malidp_write32(d71->gcu_addr, BLK_IRQ_CLEAR, raw_status);
malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL);
malidp_write32(gcu, BLK_CONTROL, GCU_CONTROL_SRST);
malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);