media5200_irq
irq_set_chip_data(virq, &media5200_irq);
media5200_irq.regs = of_iomap(fpga_np, 0);
if (!media5200_irq.regs)
pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
spin_lock_init(&media5200_irq.lock);
media5200_irq.irqhost = irq_domain_create_linear(of_fwnode_handle(fpga_np),
MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);
if (!media5200_irq.irqhost)
irq_set_handler_data(cascade_virq, &media5200_irq);
struct media5200_irq media5200_irq;
spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags);
spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags);
status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
generic_handle_domain_irq(media5200_irq.irqhost, val - 1);