drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

13

void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

16

mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_CLEAR,

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

18

mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

46

struct mdp_kms *mdp_kms = to_mdp_kms(kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

47

struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

54

mdp_irq_register(mdp_kms, error_handler);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

69

struct mdp_kms *mdp_kms = to_mdp_kms(kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

70

struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c

81

mdp_dispatch_irqs(mdp_kms, status);

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

152

void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h

20

struct mdp_kms base;

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

15

void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

18

mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR,

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

20

mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

50

struct mdp_kms *mdp_kms = to_mdp_kms(kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

51

struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

62

mdp_irq_register(mdp_kms, error_handler);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

80

struct mdp_kms *mdp_kms = to_mdp_kms(kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

81

struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);

drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c

92

mdp_dispatch_irqs(mdp_kms, status);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

21

struct mdp_kms base;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

263

void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,

drivers/gpu/drm/msm/disp/mdp_kms.c

102

void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq)

drivers/gpu/drm/msm/disp/mdp_kms.c

111

list_add(&irq->node, &mdp_kms->irq_list);

drivers/gpu/drm/msm/disp/mdp_kms.c

112

needs_update = !mdp_kms->in_irq;

drivers/gpu/drm/msm/disp/mdp_kms.c

118

mdp_irq_update(mdp_kms);

drivers/gpu/drm/msm/disp/mdp_kms.c

121

void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq)

drivers/gpu/drm/msm/disp/mdp_kms.c

131

needs_update = !mdp_kms->in_irq;

drivers/gpu/drm/msm/disp/mdp_kms.c

137

mdp_irq_update(mdp_kms);

drivers/gpu/drm/msm/disp/mdp_kms.c

21

static void update_irq(struct mdp_kms *mdp_kms)

drivers/gpu/drm/msm/disp/mdp_kms.c

24

uint32_t irqmask = mdp_kms->vblank_mask;

drivers/gpu/drm/msm/disp/mdp_kms.c

28

list_for_each_entry(irq, &mdp_kms->irq_list, node)

drivers/gpu/drm/msm/disp/mdp_kms.c

31

mdp_kms->funcs->set_irqmask(mdp_kms, irqmask, mdp_kms->cur_irq_mask);

drivers/gpu/drm/msm/disp/mdp_kms.c

32

mdp_kms->cur_irq_mask = irqmask;

drivers/gpu/drm/msm/disp/mdp_kms.c

38

void mdp_irq_update(struct mdp_kms *mdp_kms)

drivers/gpu/drm/msm/disp/mdp_kms.c

42

update_irq(mdp_kms);

drivers/gpu/drm/msm/disp/mdp_kms.c

46

void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status)

drivers/gpu/drm/msm/disp/mdp_kms.c

52

mdp_kms->in_irq = true;

drivers/gpu/drm/msm/disp/mdp_kms.c

53

list_for_each_entry_safe(handler, n, &mdp_kms->irq_list, node) {

drivers/gpu/drm/msm/disp/mdp_kms.c

60

mdp_kms->in_irq = false;

drivers/gpu/drm/msm/disp/mdp_kms.c

61

update_irq(mdp_kms);

drivers/gpu/drm/msm/disp/mdp_kms.c

66

void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable)

drivers/gpu/drm/msm/disp/mdp_kms.c

72

mdp_kms->vblank_mask |= mask;

drivers/gpu/drm/msm/disp/mdp_kms.c

74

mdp_kms->vblank_mask &= ~mask;

drivers/gpu/drm/msm/disp/mdp_kms.c

75

update_irq(mdp_kms);

drivers/gpu/drm/msm/disp/mdp_kms.c

87

void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask)

drivers/gpu/drm/msm/disp/mdp_kms.c

96

mdp_irq_register(mdp_kms, &wait.irq);

drivers/gpu/drm/msm/disp/mdp_kms.c

99

mdp_irq_unregister(mdp_kms, &wait.irq);

drivers/gpu/drm/msm/disp/mdp_kms.h

19

struct mdp_kms;

drivers/gpu/drm/msm/disp/mdp_kms.h

23

void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask,

drivers/gpu/drm/msm/disp/mdp_kms.h

38

#define to_mdp_kms(x) container_of(x, struct mdp_kms, base)

drivers/gpu/drm/msm/disp/mdp_kms.h

40

static inline int mdp_kms_init(struct mdp_kms *mdp_kms,

drivers/gpu/drm/msm/disp/mdp_kms.h

43

mdp_kms->funcs = funcs;

drivers/gpu/drm/msm/disp/mdp_kms.h

44

INIT_LIST_HEAD(&mdp_kms->irq_list);

drivers/gpu/drm/msm/disp/mdp_kms.h

45

return msm_kms_init(&mdp_kms->base, &funcs->base);

drivers/gpu/drm/msm/disp/mdp_kms.h

48

static inline void mdp_kms_destroy(struct mdp_kms *mdp_kms)

drivers/gpu/drm/msm/disp/mdp_kms.h

50

msm_kms_destroy(&mdp_kms->base);

drivers/gpu/drm/msm/disp/mdp_kms.h

70

void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status);

drivers/gpu/drm/msm/disp/mdp_kms.h

71

void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable);

drivers/gpu/drm/msm/disp/mdp_kms.h

72

void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);

drivers/gpu/drm/msm/disp/mdp_kms.h

73

void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq);

drivers/gpu/drm/msm/disp/mdp_kms.h

74

void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq);

drivers/gpu/drm/msm/disp/mdp_kms.h

75

void mdp_irq_update(struct mdp_kms *mdp_kms);