drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

129

struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c

147

struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1085

struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

1296

struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

141

struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

215

struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

587

struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

95

struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

953

struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

136

static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

169

int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

184

struct mdp5_pipeline *pipeline)

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

228

struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

251

int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

350

int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

473

static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

537

struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h

31

struct mdp5_pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h

32

int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h

33

int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h

36

int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h

54

int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h

71

u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

125

struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c

160

struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

121

struct mdp5_pipeline pipeline;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

284

struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

433

struct mdp5_pipeline *pipeline =