Symbol: mdp5_ctl
drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c
127
struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c
145
struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
1235
struct mdp5_ctl *ctl = mdp5_cstate->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
1276
struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
143
struct mdp5_ctl *ctl = mdp5_cstate->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
224
struct mdp5_ctl *ctl = mdp5_cstate->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
94
struct mdp5_ctl *ctl = mdp5_cstate->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
959
struct mdp5_ctl *ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
136
static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
169
int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
183
static bool start_signal_needed(struct mdp5_ctl *ctl,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
208
static void send_start_signal(struct mdp5_ctl *ctl)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
227
int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
251
int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
332
static void mdp5_ctl_reset_blend_regs(struct mdp5_ctl *ctl)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
350
int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
473
static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
488
static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
53
struct mdp5_ctl *pair; /* Paired CTL to be flushed together */
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
536
u32 mdp5_ctl_commit(struct mdp5_ctl *ctl,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
581
u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
586
int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
594
int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
633
struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
636
struct mdp5_ctl *ctl = NULL;
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
677
struct mdp5_ctl *ctl = &ctl_mgr->ctls[c];
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
718
struct mdp5_ctl *ctl = &ctl_mgr->ctls[c];
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
72
struct mdp5_ctl ctls[MAX_CTL];
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
84
void ctl_write(struct mdp5_ctl *ctl, u32 reg, u32 data)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c
93
u32 ctl_read(struct mdp5_ctl *ctl, u32 reg)
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
26
struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
28
int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
32
int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
33
int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
36
int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
38
int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
54
int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
71
u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h
73
u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
124
struct mdp5_ctl *ctl = mdp5_encoder->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
158
struct mdp5_ctl *ctl = mdp5_encoder->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
223
struct mdp5_ctl *ctl = mdp5_encoder->ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
286
struct mdp5_ctl *ctl)
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
268
struct mdp5_ctl *ctl)
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
306
struct mdp5_ctl *ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
120
struct mdp5_ctl *ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
167
struct mdp5_ctl *ctl;
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
280
struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
292
struct mdp5_interface *intf, struct mdp5_ctl *ctl);
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
432
struct mdp5_ctl *ctl;