Symbol: mdp4_lcdc_encoder
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
204
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
215
mdp4_lcdc_encoder->pixclock = mode->clock * 1000;
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
217
DBG("pixclock=%lu", mdp4_lcdc_encoder->pixclock);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
24
#define to_mdp4_lcdc_encoder(x) container_of(x, struct mdp4_lcdc_encoder, base)
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
261
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
265
if (WARN_ON(!mdp4_lcdc_encoder->enabled))
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
280
clk_disable_unprepare(mdp4_lcdc_encoder->lcdc_clk);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
282
regulator_bulk_disable(ARRAY_SIZE(mdp4_lcdc_encoder->regs),
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
283
mdp4_lcdc_encoder->regs);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
285
mdp4_lcdc_encoder->enabled = false;
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
291
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
293
unsigned long pc = mdp4_lcdc_encoder->pixclock;
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
298
if (WARN_ON(mdp4_lcdc_encoder->enabled))
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
316
ret = regulator_bulk_enable(ARRAY_SIZE(mdp4_lcdc_encoder->regs),
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
317
mdp4_lcdc_encoder->regs);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
322
ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
325
ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
333
mdp4_lcdc_encoder->enabled = true;
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
340
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
345
actual = clk_round_rate(mdp4_lcdc_encoder->lcdc_clk, requested);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
366
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder;
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
369
mdp4_lcdc_encoder = drmm_encoder_alloc(dev, struct mdp4_lcdc_encoder, base,
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
371
if (IS_ERR(mdp4_lcdc_encoder))
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
372
return ERR_CAST(mdp4_lcdc_encoder);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
374
encoder = &mdp4_lcdc_encoder->base;
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
378
mdp4_lcdc_encoder->lcdc_clk = mdp4_get_lcdc_clock(dev);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
379
if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) {
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
381
return ERR_CAST(mdp4_lcdc_encoder->lcdc_clk);
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
385
mdp4_lcdc_encoder->regs[0].supply = "lvds-vccs-3p3v";
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
386
mdp4_lcdc_encoder->regs[1].supply = "lvds-pll-vdda";
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
387
mdp4_lcdc_encoder->regs[2].supply = "lvds-vdda";
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
390
ARRAY_SIZE(mdp4_lcdc_encoder->regs),
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
391
mdp4_lcdc_encoder->regs);