drivers/clk/qcom/ipq-cmn-pll.c

114

CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

115

CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),

drivers/clk/qcom/ipq-cmn-pll.c

116

CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

121

CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

122

CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),

drivers/clk/qcom/ipq-cmn-pll.c

123

CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),

drivers/clk/qcom/ipq-cmn-pll.c

124

CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

125

CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

126

CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

127

CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

128

CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

129

CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

134

CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

135

CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),

drivers/clk/qcom/ipq-cmn-pll.c

136

CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),

drivers/clk/qcom/ipq-cmn-pll.c

137

CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

138

CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

139

CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

140

CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

141

CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),

drivers/clk/qcom/ipq-cmn-pll.c

142

CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),