ltq_r32
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
i->partnum = (ltq_r32(FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
i->rev = (ltq_r32(FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
i->srev = ((ltq_r32(FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
type = (ltq_r32(FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
#define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x))
#define status_r32(x) ltq_r32(status_membase + (x))
ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
#define gptu_r32(x) ltq_r32(gptu_membase + (x))
i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
#define pmu_r32(x) ltq_r32(pmu_membase + (x))
*data = ltq_r32(((u32 *)(cfg_base)));
temp = ltq_r32(((u32 *)(cfg_base)));
#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
#define pad_r32(p, reg) ltq_r32(p + reg)
#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))