mcs_reg_write
mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT, cpm_intr);
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT, cpm_intr);
mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_INTR_RW, 0);
mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT, bbe_intr);
mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_INTR_RW, 0);
mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT, bbe_intr);
mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_INTR_RW, 0);
mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT, pab_intr);
mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_INTR_RW, 0);
mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT, pab_intr);
mcs_reg_write(mcs, MCSX_IP_INT, BIT_ULL(0));
mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0));
mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0));
mcs_reg_write(mcs, MCSX_TOP_SLAVE_INT_SUM_ENB,
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT_ENB, 0x7ULL);
mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT_ENB, 0x7FULL);
mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_ENB, 0xFFULL);
mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_ENB, 0xFFULL);
mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_ENB, 0xFFFFFULL);
mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_ENB, 0xFFFFFULL);
mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id),
mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id), val);
mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id),
mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, val);
mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id), val);
mcs_reg_write(mcs, reg, reset & 0x1);
mcs_reg_write(mcs, reg, (u64)mode);
mcs_reg_write(mcs, reg, (u64)mode);
mcs_reg_write(mcs, reg, pn->threshold);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, 0);
mcs_reg_write(mcs, reg, 0xe000e);
mcs_reg_write(mcs, reg, 0);
mcs_reg_write(mcs, MCSX_LINK_LMACX_CFG(lmac), cfg);
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, mcs_reg_read(mcs, MCSX_MIL_GLOBAL) & ~BIT_ULL(5));
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
mcs_reg_write(mcs, MCSX_CSE_RX_SLAVE_STATS_CLEAR, 0x1F);
mcs_reg_write(mcs, MCSX_CSE_TX_SLAVE_STATS_CLEAR, 0x1F);
mcs_reg_write(mcs, MCSX_IP_MODE, BIT_ULL(3));
mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_ENTRY, 0xe4);
mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_LEN, 4);
mcs_reg_write(mcs, reg, BIT_ULL(0));
mcs_reg_write(mcs, reg, 0x0);
mcs_reg_write(mcs, reg, next_pn);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, plcy[reg_id]);
mcs_reg_write(mcs, reg, plcy[reg_id]);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(0, sc_id), sci);
mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(1, sc_id), secy);
mcs_reg_write(mcs, reg, plcy);
mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(secy_id), 0x0ull);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, data[reg_id]);
mcs_reg_write(mcs, reg, mask[reg_id]);
mcs_reg_write(mcs, reg, data[reg_id]);
mcs_reg_write(mcs, reg, mask[reg_id]);
mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0));
mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0));
mcs_reg_write(mcs, reg, dis);
mcs_reg_write(mcs, reg, dis);
mcs_reg_write(mcs, reg, req->data0);
mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data2);
mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, req->data2);
mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0));
mcs_reg_write(mcs, reg, enb);
mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1C, BIT_ULL(0));
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(map->sc_id), map->sa_index0_vld);
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(map->sc_id), map->sa_index1_vld);
mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(map->sc_id), map->tx_sa_active);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, map->sci);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, reg, val);
mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, cfg);
mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PORT_CFGX(port), cfg);