arch/mips/lantiq/xway/dma.c

103

ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

115

ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

116

ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);

arch/mips/lantiq/xway/dma.c

135

ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

137

ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

152

ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);

arch/mips/lantiq/xway/dma.c

167

ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);

arch/mips/lantiq/xway/dma.c

194

ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),

arch/mips/lantiq/xway/dma.c

204

ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),

arch/mips/lantiq/xway/dma.c

208

ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),

arch/mips/lantiq/xway/dma.c

212

ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),

arch/mips/lantiq/xway/dma.c

221

ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),

arch/mips/lantiq/xway/dma.c

225

ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),

arch/mips/lantiq/xway/dma.c

229

ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),

arch/mips/lantiq/xway/dma.c

255

ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);

arch/mips/lantiq/xway/dma.c

269

ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);

arch/mips/lantiq/xway/dma.c

67

ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);

arch/mips/lantiq/xway/dma.c

79

ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);