drivers/gpu/drm/i915/display/intel_dp_link_training.c

1005

lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1011

lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1017

lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

108

lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1092

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1100

lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1116

lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1148

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1156

lt_dbg(intel_dp, DP_PHY_DPRX, "Channel EQ check failed. cannot continue POST_LT_ADJ_REQ\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1163

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1171

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1179

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1243

lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1283

lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1312

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1446

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1457

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1462

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1480

lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1485

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1597

lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1647

lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1699

lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1742

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1808

lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

182

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1829

lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1844

lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1864

lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

495

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

501

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

576

lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

60

lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \

drivers/gpu/drm/i915/display/intel_dp_link_training.c

614

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

620

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

819

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

822

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

837

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

840

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

89

lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

894

lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

901

lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

904

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

93

lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

948

lt_dbg(intel_dp, dp_phy,