drivers/gpu/drm/mcde/mcde_clk_div.c

101

cr = readl(mcde->regs + cdiv->cr);

drivers/gpu/drm/mcde/mcde_clk_div.c

12

struct mcde *mcde;

drivers/gpu/drm/mcde/mcde_clk_div.c

142

int mcde_init_clock_divider(struct mcde *mcde)

drivers/gpu/drm/mcde/mcde_clk_div.c

144

struct device *dev = mcde->dev;

drivers/gpu/drm/mcde/mcde_clk_div.c

164

spin_lock_init(&mcde->fifo_crx1_lock);

drivers/gpu/drm/mcde/mcde_clk_div.c

165

parent_name = __clk_get_name(mcde->lcd_clk);

drivers/gpu/drm/mcde/mcde_clk_div.c

175

fifoa->mcde = mcde;

drivers/gpu/drm/mcde/mcde_clk_div.c

183

mcde->fifoa_clk = fifoa->hw.clk;

drivers/gpu/drm/mcde/mcde_clk_div.c

185

fifob->mcde = mcde;

drivers/gpu/drm/mcde/mcde_clk_div.c

193

mcde->fifob_clk = fifob->hw.clk;

drivers/gpu/drm/mcde/mcde_clk_div.c

20

struct mcde *mcde = cdiv->mcde;

drivers/gpu/drm/mcde/mcde_clk_div.c

23

spin_lock(&mcde->fifo_crx1_lock);

drivers/gpu/drm/mcde/mcde_clk_div.c

24

val = readl(mcde->regs + cdiv->cr);

drivers/gpu/drm/mcde/mcde_clk_div.c

38

writel(val, mcde->regs + cdiv->cr);

drivers/gpu/drm/mcde/mcde_clk_div.c

39

spin_unlock(&mcde->fifo_crx1_lock);

drivers/gpu/drm/mcde/mcde_clk_div.c

89

struct mcde *mcde = cdiv->mcde;

drivers/gpu/drm/mcde/mcde_clk_div.c

98

if (!regulator_is_enabled(mcde->epod))

drivers/gpu/drm/mcde/mcde_display.c

102

if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {

drivers/gpu/drm/mcde/mcde_display.c

1028

writel(val, mcde->regs + MCDE_CONF0);

drivers/gpu/drm/mcde/mcde_display.c

103

spin_lock(&mcde->flow_lock);

drivers/gpu/drm/mcde/mcde_display.c

1031

writel(0, mcde->regs + MCDE_TVCRA);

drivers/gpu/drm/mcde/mcde_display.c

1036

writel(val, mcde->regs + MCDE_TVBL1A);

drivers/gpu/drm/mcde/mcde_display.c

1038

writel(val, mcde->regs + MCDE_TVBL2A);

drivers/gpu/drm/mcde/mcde_display.c

104

if (--mcde->flow_active == 0) {

drivers/gpu/drm/mcde/mcde_display.c

1044

writel(val, mcde->regs + MCDE_TVDVOA);

drivers/gpu/drm/mcde/mcde_display.c

1047

writel((hbp - 1), mcde->regs + MCDE_TVTIM1A);

drivers/gpu/drm/mcde/mcde_display.c

105

dev_dbg(mcde->dev, "TE0 IRQ\n");

drivers/gpu/drm/mcde/mcde_display.c

1052

writel(val, mcde->regs + MCDE_TVLBALWA);

drivers/gpu/drm/mcde/mcde_display.c

1055

writel(0, mcde->regs + MCDE_TVISLA);

drivers/gpu/drm/mcde/mcde_display.c

1056

writel(0, mcde->regs + MCDE_TVBLUA);

drivers/gpu/drm/mcde/mcde_display.c

1068

writel(val, mcde->regs + MCDE_LCDTIM1A);

drivers/gpu/drm/mcde/mcde_display.c

107

val = readl(mcde->regs + MCDE_CRA0);

drivers/gpu/drm/mcde/mcde_display.c

1071

static void mcde_setup_dsi(struct mcde *mcde, const struct drm_display_mode *mode,

drivers/gpu/drm/mcde/mcde_display.c

1084

dev_info(mcde->dev, "output in %s mode, format %dbpp\n",

drivers/gpu/drm/mcde/mcde_display.c

1085

(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ?

drivers/gpu/drm/mcde/mcde_display.c

1087

mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format));

drivers/gpu/drm/mcde/mcde_display.c

1089

mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8;

drivers/gpu/drm/mcde/mcde_display.c

109

writel(val, mcde->regs + MCDE_CRA0);

drivers/gpu/drm/mcde/mcde_display.c

1090

dev_info(mcde->dev, "Overlay CPP: %d bytes, DSI formatter CPP %d bytes\n",

drivers/gpu/drm/mcde/mcde_display.c

1107

writel(val, mcde->regs + MCDE_CONF0);

drivers/gpu/drm/mcde/mcde_display.c

111

spin_unlock(&mcde->flow_lock);

drivers/gpu/drm/mcde/mcde_display.c

1121

if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {

drivers/gpu/drm/mcde/mcde_display.c

1129

dev_dbg(mcde->dev, "FIFO watermark after flooring: %d bytes\n",

drivers/gpu/drm/mcde/mcde_display.c

1131

dev_dbg(mcde->dev, "Packet divisor: %d bytes\n", pkt_div);

drivers/gpu/drm/mcde/mcde_display.c

1136

if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO))

drivers/gpu/drm/mcde/mcde_display.c

1139

dev_dbg(mcde->dev, "DSI packet size: %d * %d bytes per line\n",

drivers/gpu/drm/mcde/mcde_display.c

1141

dev_dbg(mcde->dev, "Overlay frame size: %u bytes\n",

drivers/gpu/drm/mcde/mcde_display.c

1145

dev_dbg(mcde->dev, "Formatter frame size: %u bytes\n", formatter_frame);

drivers/gpu/drm/mcde/mcde_display.c

1159

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_display.c

117

dev_dbg(mcde->dev, "chnl A vblank IRQ\n");

drivers/gpu/drm/mcde/mcde_display.c

1171

ret = regulator_enable(mcde->epod);

drivers/gpu/drm/mcde/mcde_display.c

1182

mcde_display_disable_irqs(mcde);

drivers/gpu/drm/mcde/mcde_display.c

1183

writel(0, mcde->regs + MCDE_IMSCERR);

drivers/gpu/drm/mcde/mcde_display.c

1184

writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);

drivers/gpu/drm/mcde/mcde_display.c

1186

if (mcde->dpi_output)

drivers/gpu/drm/mcde/mcde_display.c

1187

mcde_setup_dpi(mcde, mode, &fifo_wtrmrk);

drivers/gpu/drm/mcde/mcde_display.c

1189

mcde_setup_dsi(mcde, mode, cpp, &fifo_wtrmrk,

drivers/gpu/drm/mcde/mcde_display.c

1192

mcde->stride = mode->hdisplay * cpp;

drivers/gpu/drm/mcde/mcde_display.c

1194

mcde->stride);

drivers/gpu/drm/mcde/mcde_display.c

1197

mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0);

drivers/gpu/drm/mcde/mcde_display.c

1206

mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format);

drivers/gpu/drm/mcde/mcde_display.c

121

dev_dbg(mcde->dev, "chnl B vblank IRQ\n");

drivers/gpu/drm/mcde/mcde_display.c

1213

mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0,

drivers/gpu/drm/mcde/mcde_display.c

1220

mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode);

drivers/gpu/drm/mcde/mcde_display.c

1222

if (mcde->dpi_output) {

drivers/gpu/drm/mcde/mcde_display.c

1226

mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DPI_FORMATTER_0,

drivers/gpu/drm/mcde/mcde_display.c

1230

lcd_freq = clk_round_rate(mcde->fifoa_clk, mode->clock * 1000);

drivers/gpu/drm/mcde/mcde_display.c

1231

ret = clk_set_rate(mcde->fifoa_clk, lcd_freq);

drivers/gpu/drm/mcde/mcde_display.c

1233

dev_err(mcde->dev, "failed to set LCD clock rate %lu Hz\n",

drivers/gpu/drm/mcde/mcde_display.c

1235

ret = clk_prepare_enable(mcde->fifoa_clk);

drivers/gpu/drm/mcde/mcde_display.c

1237

dev_err(mcde->dev, "failed to enable FIFO A DPI clock\n");

drivers/gpu/drm/mcde/mcde_display.c

1240

dev_info(mcde->dev, "LCD FIFO A clk rate %lu Hz\n",

drivers/gpu/drm/mcde/mcde_display.c

1241

clk_get_rate(mcde->fifoa_clk));

drivers/gpu/drm/mcde/mcde_display.c

1244

mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0,

drivers/gpu/drm/mcde/mcde_display.c

125

dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n");

drivers/gpu/drm/mcde/mcde_display.c

1251

mcde_dsi_enable(mcde->bridge);

drivers/gpu/drm/mcde/mcde_display.c

1254

mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0,

drivers/gpu/drm/mcde/mcde_display.c

1258

switch (mcde->flow_mode) {

drivers/gpu/drm/mcde/mcde_display.c

1267

writel(val, mcde->regs + MCDE_VSCRC0);

drivers/gpu/drm/mcde/mcde_display.c

1269

val = readl(mcde->regs + MCDE_CRC);

drivers/gpu/drm/mcde/mcde_display.c

127

dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n");

drivers/gpu/drm/mcde/mcde_display.c

1271

writel(val, mcde->regs + MCDE_CRC);

drivers/gpu/drm/mcde/mcde_display.c

1288

if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) {

drivers/gpu/drm/mcde/mcde_display.c

1289

mcde_enable_fifo(mcde, MCDE_FIFO_A);

drivers/gpu/drm/mcde/mcde_display.c

129

dev_dbg(mcde->dev, "chnl C0 TE IRQ\n");

drivers/gpu/drm/mcde/mcde_display.c

1290

dev_dbg(mcde->dev, "started MCDE video FIFO flow\n");

drivers/gpu/drm/mcde/mcde_display.c

1294

val = readl(mcde->regs + MCDE_CR);

drivers/gpu/drm/mcde/mcde_display.c

1296

writel(val, mcde->regs + MCDE_CR);

drivers/gpu/drm/mcde/mcde_display.c

1305

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_display.c

131

dev_dbg(mcde->dev, "chnl C1 TE IRQ\n");

drivers/gpu/drm/mcde/mcde_display.c

1312

mcde_disable_fifo(mcde, MCDE_FIFO_A, true);

drivers/gpu/drm/mcde/mcde_display.c

1314

if (mcde->dpi_output) {

drivers/gpu/drm/mcde/mcde_display.c

1315

clk_disable_unprepare(mcde->fifoa_clk);

drivers/gpu/drm/mcde/mcde_display.c

1318

mcde_dsi_disable(mcde->bridge);

drivers/gpu/drm/mcde/mcde_display.c

132

writel(mispp, mcde->regs + MCDE_RISPP);

drivers/gpu/drm/mcde/mcde_display.c

1330

ret = regulator_disable(mcde->epod);

drivers/gpu/drm/mcde/mcde_display.c

1339

static void mcde_start_flow(struct mcde *mcde)

drivers/gpu/drm/mcde/mcde_display.c

1342

if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW)

drivers/gpu/drm/mcde/mcde_display.c

1343

mcde_dsi_te_request(mcde->mdsi);

drivers/gpu/drm/mcde/mcde_display.c

1346

mcde_enable_fifo(mcde, MCDE_FIFO_A);

drivers/gpu/drm/mcde/mcde_display.c

135

drm_crtc_handle_vblank(&mcde->pipe.crtc);

drivers/gpu/drm/mcde/mcde_display.c

1355

if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {

drivers/gpu/drm/mcde/mcde_display.c

1358

mcde->regs + MCDE_CHNL0SYNCHSW);

drivers/gpu/drm/mcde/mcde_display.c

1367

mcde_disable_fifo(mcde, MCDE_FIFO_A, true);

drivers/gpu/drm/mcde/mcde_display.c

1370

dev_dbg(mcde->dev, "started MCDE FIFO flow\n");

drivers/gpu/drm/mcde/mcde_display.c

1373

static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address)

drivers/gpu/drm/mcde/mcde_display.c

1376

writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0);

drivers/gpu/drm/mcde/mcde_display.c

138

dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl);

drivers/gpu/drm/mcde/mcde_display.c

1381

writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1);

drivers/gpu/drm/mcde/mcde_display.c

1389

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_display.c

139

writel(misovl, mcde->regs + MCDE_RISOVL);

drivers/gpu/drm/mcde/mcde_display.c

1412

dev_dbg(mcde->dev, "arm vblank event\n");

drivers/gpu/drm/mcde/mcde_display.c

1415

dev_dbg(mcde->dev, "insert fake vblank event\n");

drivers/gpu/drm/mcde/mcde_display.c

142

dev_info(mcde->dev, "some stray channel error IRQ %08x\n",

drivers/gpu/drm/mcde/mcde_display.c

1428

mcde_set_extsrc(mcde, drm_fb_dma_get_gem_addr(fb, pstate, 0));

drivers/gpu/drm/mcde/mcde_display.c

1429

dev_info_once(mcde->dev, "first update of display contents\n");

drivers/gpu/drm/mcde/mcde_display.c

1434

if (mcde->flow_active == 0)

drivers/gpu/drm/mcde/mcde_display.c

1435

mcde_start_flow(mcde);

drivers/gpu/drm/mcde/mcde_display.c

144

writel(mischnl, mcde->regs + MCDE_RISCHNL);

drivers/gpu/drm/mcde/mcde_display.c

1442

dev_info(mcde->dev, "ignored a display update\n");

drivers/gpu/drm/mcde/mcde_display.c

1450

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_display.c

1460

writel(val, mcde->regs + MCDE_IMSCPP);

drivers/gpu/drm/mcde/mcde_display.c

1469

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_display.c

147

void mcde_display_disable_irqs(struct mcde *mcde)

drivers/gpu/drm/mcde/mcde_display.c

1472

writel(0, mcde->regs + MCDE_IMSCPP);

drivers/gpu/drm/mcde/mcde_display.c

1474

writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);

drivers/gpu/drm/mcde/mcde_display.c

1488

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_display.c

150

writel(0, mcde->regs + MCDE_IMSCPP);

drivers/gpu/drm/mcde/mcde_display.c

1509

ret = mcde_init_clock_divider(mcde);

drivers/gpu/drm/mcde/mcde_display.c

151

writel(0, mcde->regs + MCDE_IMSCOVL);

drivers/gpu/drm/mcde/mcde_display.c

1513

ret = drm_simple_display_pipe_init(drm, &mcde->pipe,

drivers/gpu/drm/mcde/mcde_display.c

1517

mcde->connector);

drivers/gpu/drm/mcde/mcde_display.c

152

writel(0, mcde->regs + MCDE_IMSCCHNL);

drivers/gpu/drm/mcde/mcde_display.c

155

writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);

drivers/gpu/drm/mcde/mcde_display.c

156

writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL);

drivers/gpu/drm/mcde/mcde_display.c

157

writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL);

drivers/gpu/drm/mcde/mcde_display.c

197

static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src,

drivers/gpu/drm/mcde/mcde_display.c

325

dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",

drivers/gpu/drm/mcde/mcde_display.c

329

writel(val, mcde->regs + conf);

drivers/gpu/drm/mcde/mcde_display.c

334

writel(val, mcde->regs + cr);

drivers/gpu/drm/mcde/mcde_display.c

339

static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl,

drivers/gpu/drm/mcde/mcde_display.c

409

writel(val, mcde->regs + conf1);

drivers/gpu/drm/mcde/mcde_display.c

433

dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",

drivers/gpu/drm/mcde/mcde_display.c

461

dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n",

drivers/gpu/drm/mcde/mcde_display.c

464

writel(val, mcde->regs + conf2);

drivers/gpu/drm/mcde/mcde_display.c

467

writel(mcde->stride, mcde->regs + ljinc);

drivers/gpu/drm/mcde/mcde_display.c

469

writel(0, mcde->regs + crop);

drivers/gpu/drm/mcde/mcde_display.c

481

writel(val, mcde->regs + cr);

drivers/gpu/drm/mcde/mcde_display.c

488

writel(val, mcde->regs + comp);

drivers/gpu/drm/mcde/mcde_display.c

491

static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch,

drivers/gpu/drm/mcde/mcde_display.c

534

switch (mcde->flow_mode) {

drivers/gpu/drm/mcde/mcde_display.c

572

dev_err(mcde->dev, "unknown flow mode %d\n",

drivers/gpu/drm/mcde/mcde_display.c

573

mcde->flow_mode);

drivers/gpu/drm/mcde/mcde_display.c

577

writel(val, mcde->regs + sync);

drivers/gpu/drm/mcde/mcde_display.c

582

writel(val, mcde->regs + conf);

drivers/gpu/drm/mcde/mcde_display.c

590

writel(val, mcde->regs + stat);

drivers/gpu/drm/mcde/mcde_display.c

591

writel(0, mcde->regs + bgcol);

drivers/gpu/drm/mcde/mcde_display.c

597

mcde->regs + mux);

drivers/gpu/drm/mcde/mcde_display.c

601

mcde->regs + mux);

drivers/gpu/drm/mcde/mcde_display.c

609

if (mcde->dpi_output) {

drivers/gpu/drm/mcde/mcde_display.c

613

dev_info(mcde->dev, "stripwidth: %d\n", stripwidth);

drivers/gpu/drm/mcde/mcde_display.c

622

writel(val, mcde->regs + MCDE_SYNCHCONFA);

drivers/gpu/drm/mcde/mcde_display.c

625

writel(val, mcde->regs + MCDE_SYNCHCONFB);

drivers/gpu/drm/mcde/mcde_display.c

631

static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo,

drivers/gpu/drm/mcde/mcde_display.c

696

writel(val, mcde->regs + ctrl);

drivers/gpu/drm/mcde/mcde_display.c

701

writel(val, mcde->regs + cr0);

drivers/gpu/drm/mcde/mcde_display.c

703

spin_lock(&mcde->fifo_crx1_lock);

drivers/gpu/drm/mcde/mcde_display.c

704

val = readl(mcde->regs + cr1);

drivers/gpu/drm/mcde/mcde_display.c

709

if (mcde->dpi_output) {

drivers/gpu/drm/mcde/mcde_display.c

710

struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);

drivers/gpu/drm/mcde/mcde_display.c

715

dev_info(mcde->dev, "panel does not specify bus format, assume RGB888\n");

drivers/gpu/drm/mcde/mcde_display.c

735

dev_err(mcde->dev, "unknown bus format, assume RGB888\n");

drivers/gpu/drm/mcde/mcde_display.c

745

writel(val, mcde->regs + cr1);

drivers/gpu/drm/mcde/mcde_display.c

746

spin_unlock(&mcde->fifo_crx1_lock);

drivers/gpu/drm/mcde/mcde_display.c

749

static void mcde_configure_dsi_formatter(struct mcde *mcde,

drivers/gpu/drm/mcde/mcde_display.c

75

void mcde_display_irq(struct mcde *mcde)

drivers/gpu/drm/mcde/mcde_display.c

791

dev_err(mcde->dev, "tried to configure a non-DSI formatter as DSI\n");

drivers/gpu/drm/mcde/mcde_display.c

800

if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)

drivers/gpu/drm/mcde/mcde_display.c

802

switch (mcde->mdsi->format) {

drivers/gpu/drm/mcde/mcde_display.c

81

mispp = readl(mcde->regs + MCDE_MISPP);

drivers/gpu/drm/mcde/mcde_display.c

812

dev_err(mcde->dev,

drivers/gpu/drm/mcde/mcde_display.c

82

misovl = readl(mcde->regs + MCDE_MISOVL);

drivers/gpu/drm/mcde/mcde_display.c

822

dev_err(mcde->dev, "unknown DSI format\n");

drivers/gpu/drm/mcde/mcde_display.c

825

writel(val, mcde->regs + conf0);

drivers/gpu/drm/mcde/mcde_display.c

827

writel(formatter_frame, mcde->regs + frame);

drivers/gpu/drm/mcde/mcde_display.c

828

writel(pkt_size, mcde->regs + pkt);

drivers/gpu/drm/mcde/mcde_display.c

829

writel(0, mcde->regs + sync);

drivers/gpu/drm/mcde/mcde_display.c

83

mischnl = readl(mcde->regs + MCDE_MISCHNL);

drivers/gpu/drm/mcde/mcde_display.c

835

writel(val, mcde->regs + cmdw);

drivers/gpu/drm/mcde/mcde_display.c

841

writel(0, mcde->regs + delay0);

drivers/gpu/drm/mcde/mcde_display.c

842

writel(0, mcde->regs + delay1);

drivers/gpu/drm/mcde/mcde_display.c

845

static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo)

drivers/gpu/drm/mcde/mcde_display.c

858

dev_err(mcde->dev, "cannot enable FIFO %c\n",

drivers/gpu/drm/mcde/mcde_display.c

863

spin_lock(&mcde->flow_lock);

drivers/gpu/drm/mcde/mcde_display.c

864

val = readl(mcde->regs + cr);

drivers/gpu/drm/mcde/mcde_display.c

866

writel(val, mcde->regs + cr);

drivers/gpu/drm/mcde/mcde_display.c

867

mcde->flow_active++;

drivers/gpu/drm/mcde/mcde_display.c

868

spin_unlock(&mcde->flow_lock);

drivers/gpu/drm/mcde/mcde_display.c

871

static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo,

drivers/gpu/drm/mcde/mcde_display.c

886

dev_err(mcde->dev, "cannot disable FIFO %c\n",

drivers/gpu/drm/mcde/mcde_display.c

891

spin_lock(&mcde->flow_lock);

drivers/gpu/drm/mcde/mcde_display.c

892

val = readl(mcde->regs + cr);

drivers/gpu/drm/mcde/mcde_display.c

894

writel(val, mcde->regs + cr);

drivers/gpu/drm/mcde/mcde_display.c

895

mcde->flow_active = 0;

drivers/gpu/drm/mcde/mcde_display.c

896

spin_unlock(&mcde->flow_lock);

drivers/gpu/drm/mcde/mcde_display.c

902

while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {

drivers/gpu/drm/mcde/mcde_display.c

905

dev_err(mcde->dev,

drivers/gpu/drm/mcde/mcde_display.c

916

static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo,

drivers/gpu/drm/mcde/mcde_display.c

93

if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) {

drivers/gpu/drm/mcde/mcde_display.c

947

val = readl(mcde->regs + ctrl);

drivers/gpu/drm/mcde/mcde_display.c

949

dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n");

drivers/gpu/drm/mcde/mcde_display.c

951

mcde_enable_fifo(mcde, fifo);

drivers/gpu/drm/mcde/mcde_display.c

953

writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw);

drivers/gpu/drm/mcde/mcde_display.c

955

mcde_disable_fifo(mcde, fifo, true);

drivers/gpu/drm/mcde/mcde_display.c

974

static void mcde_setup_dpi(struct mcde *mcde, const struct drm_display_mode *mode,

drivers/gpu/drm/mcde/mcde_display.c

977

struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);

drivers/gpu/drm/mcde/mcde_display.c

990

dev_info(mcde->dev, "output on DPI LCD from channel A\n");

drivers/gpu/drm/mcde/mcde_display.c

992

dev_info(mcde->dev, "HSW: %d, HFP: %d, HBP: %d, VSW: %d, VFP: %d, VBP: %d\n",

drivers/gpu/drm/mcde/mcde_drm.h

100

static inline bool mcde_flow_is_video(struct mcde *mcde)

drivers/gpu/drm/mcde/mcde_drm.h

102

return (mcde->flow_mode == MCDE_VIDEO_TE_FLOW ||

drivers/gpu/drm/mcde/mcde_drm.h

103

mcde->flow_mode == MCDE_VIDEO_FORMATTER_FLOW);

drivers/gpu/drm/mcde/mcde_drm.h

112

void mcde_display_irq(struct mcde *mcde);

drivers/gpu/drm/mcde/mcde_drm.h

113

void mcde_display_disable_irqs(struct mcde *mcde);

drivers/gpu/drm/mcde/mcde_drm.h

116

int mcde_init_clock_divider(struct mcde *mcde);

drivers/gpu/drm/mcde/mcde_drm.h

98

#define to_mcde(dev) container_of(dev, struct mcde, drm)

drivers/gpu/drm/mcde/mcde_drv.c

114

struct mcde *mcde = data;

drivers/gpu/drm/mcde/mcde_drv.c

117

val = readl(mcde->regs + MCDE_MISERR);

drivers/gpu/drm/mcde/mcde_drv.c

119

mcde_display_irq(mcde);

drivers/gpu/drm/mcde/mcde_drv.c

122

dev_info(mcde->dev, "some error IRQ\n");

drivers/gpu/drm/mcde/mcde_drv.c

123

writel(val, mcde->regs + MCDE_RISERR);

drivers/gpu/drm/mcde/mcde_drv.c

131

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_drv.c

142

if (!mcde->bridge) {

drivers/gpu/drm/mcde/mcde_drv.c

162

mcde->dpi_output = true;

drivers/gpu/drm/mcde/mcde_drv.c

163

mcde->bridge = bridge;

drivers/gpu/drm/mcde/mcde_drv.c

164

mcde->flow_mode = MCDE_DPI_FORMATTER_FLOW;

drivers/gpu/drm/mcde/mcde_drv.c

189

ret = drm_simple_display_pipe_attach_bridge(&mcde->pipe,

drivers/gpu/drm/mcde/mcde_drv.c

190

mcde->bridge);

drivers/gpu/drm/mcde/mcde_drv.c

272

struct mcde *mcde;

drivers/gpu/drm/mcde/mcde_drv.c

279

mcde = devm_drm_dev_alloc(dev, &mcde_drm_driver, struct mcde, drm);

drivers/gpu/drm/mcde/mcde_drv.c

280

if (IS_ERR(mcde))

drivers/gpu/drm/mcde/mcde_drv.c

281

return PTR_ERR(mcde);

drivers/gpu/drm/mcde/mcde_drv.c

282

drm = &mcde->drm;

drivers/gpu/drm/mcde/mcde_drv.c

283

mcde->dev = dev;

drivers/gpu/drm/mcde/mcde_drv.c

287

mcde->epod = devm_regulator_get(dev, "epod");

drivers/gpu/drm/mcde/mcde_drv.c

288

if (IS_ERR(mcde->epod)) {

drivers/gpu/drm/mcde/mcde_drv.c

289

ret = PTR_ERR(mcde->epod);

drivers/gpu/drm/mcde/mcde_drv.c

293

ret = regulator_enable(mcde->epod);

drivers/gpu/drm/mcde/mcde_drv.c

298

mcde->vana = devm_regulator_get(dev, "vana");

drivers/gpu/drm/mcde/mcde_drv.c

299

if (IS_ERR(mcde->vana)) {

drivers/gpu/drm/mcde/mcde_drv.c

300

ret = PTR_ERR(mcde->vana);

drivers/gpu/drm/mcde/mcde_drv.c

304

ret = regulator_enable(mcde->vana);

drivers/gpu/drm/mcde/mcde_drv.c

315

mcde->mcde_clk = devm_clk_get(dev, "mcde");

drivers/gpu/drm/mcde/mcde_drv.c

316

if (IS_ERR(mcde->mcde_clk)) {

drivers/gpu/drm/mcde/mcde_drv.c

318

ret = PTR_ERR(mcde->mcde_clk);

drivers/gpu/drm/mcde/mcde_drv.c

321

ret = clk_prepare_enable(mcde->mcde_clk);

drivers/gpu/drm/mcde/mcde_drv.c

326

dev_info(dev, "MCDE clk rate %lu Hz\n", clk_get_rate(mcde->mcde_clk));

drivers/gpu/drm/mcde/mcde_drv.c

328

mcde->lcd_clk = devm_clk_get(dev, "lcd");

drivers/gpu/drm/mcde/mcde_drv.c

329

if (IS_ERR(mcde->lcd_clk)) {

drivers/gpu/drm/mcde/mcde_drv.c

331

ret = PTR_ERR(mcde->lcd_clk);

drivers/gpu/drm/mcde/mcde_drv.c

334

mcde->hdmi_clk = devm_clk_get(dev, "hdmi");

drivers/gpu/drm/mcde/mcde_drv.c

335

if (IS_ERR(mcde->hdmi_clk)) {

drivers/gpu/drm/mcde/mcde_drv.c

337

ret = PTR_ERR(mcde->hdmi_clk);

drivers/gpu/drm/mcde/mcde_drv.c

341

mcde->regs = devm_platform_ioremap_resource(pdev, 0);

drivers/gpu/drm/mcde/mcde_drv.c

342

if (IS_ERR(mcde->regs)) {

drivers/gpu/drm/mcde/mcde_drv.c

354

ret = devm_request_irq(dev, irq, mcde_irq, 0, "mcde", mcde);

drivers/gpu/drm/mcde/mcde_drv.c

366

pid = readl(mcde->regs + MCDE_PID);

drivers/gpu/drm/mcde/mcde_drv.c

383

mcde_display_disable_irqs(mcde);

drivers/gpu/drm/mcde/mcde_drv.c

384

writel(0, mcde->regs + MCDE_IMSCERR);

drivers/gpu/drm/mcde/mcde_drv.c

385

writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);

drivers/gpu/drm/mcde/mcde_drv.c

419

ret = regulator_disable(mcde->epod);

drivers/gpu/drm/mcde/mcde_drv.c

435

clk_disable_unprepare(mcde->mcde_clk);

drivers/gpu/drm/mcde/mcde_drv.c

436

regulator_disable(mcde->vana);

drivers/gpu/drm/mcde/mcde_drv.c

443

clk_disable_unprepare(mcde->mcde_clk);

drivers/gpu/drm/mcde/mcde_drv.c

445

regulator_disable(mcde->vana);

drivers/gpu/drm/mcde/mcde_drv.c

447

regulator_disable(mcde->epod);

drivers/gpu/drm/mcde/mcde_drv.c

455

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_drv.c

458

clk_disable_unprepare(mcde->mcde_clk);

drivers/gpu/drm/mcde/mcde_drv.c

459

regulator_disable(mcde->vana);

drivers/gpu/drm/mcde/mcde_drv.c

460

regulator_disable(mcde->epod);

drivers/gpu/drm/mcde/mcde_dsi.c

1075

struct mcde *mcde = to_mcde(drm);

drivers/gpu/drm/mcde/mcde_dsi.c

1086

d->mcde = mcde;

drivers/gpu/drm/mcde/mcde_dsi.c

1145

mcde->bridge = &d->bridge;

drivers/gpu/drm/mcde/mcde_dsi.c

150

d->mcde->mdsi = d->mdsi;

drivers/gpu/drm/mcde/mcde_dsi.c

165

d->mcde->flow_mode = MCDE_VIDEO_FORMATTER_FLOW;

drivers/gpu/drm/mcde/mcde_dsi.c

167

d->mcde->flow_mode = MCDE_COMMAND_TE_FLOW;

drivers/gpu/drm/mcde/mcde_dsi.c

187

if (d->mcde)

drivers/gpu/drm/mcde/mcde_dsi.c

199

if (d->mcde)

drivers/gpu/drm/mcde/mcde_dsi.c

200

d->mcde->mdsi = NULL;

drivers/gpu/drm/mcde/mcde_dsi.c

40

struct mcde *mcde;