mcam_reg_write
mcam_reg_write(mcam, REG_TWSIC0, rval);
mcam_reg_write(mcam, REG_TWSIC1, rval);
mcam_reg_write(mcam, REG_TWSIC0, rval);
mcam_reg_write(mcam, REG_TWSIC1, rval);
mcam_reg_write(mcam, 0x3038, 0x8);
mcam_reg_write(mcam, 0x315c, 0x80008);
mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRS|GCSR_MRS); /* Needed? */
mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRC);
mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRS);
mcam_reg_write(mcam, REG_GL_CSR, GCSR_CCIC_EN|GCSR_SRC|GCSR_MRC);
mcam_reg_write(mcam, REG_IRQMASK, 0);
mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT|GGPIO_VAL);
mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN); /* pwr up, reset */
mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C0);
mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C1);
mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT);
mcam_reg_write(mcam, REG_IRQSTAT, TWSIIRQS);
mcam_reg_write(cam, reg->reg, reg->val);
mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
mcam_reg_write(mcam, REG_CSI2_DPHY3, mcam->dphy[0]);
mcam_reg_write(mcam, REG_CSI2_DPHY5, mcam->dphy[1]);
mcam_reg_write(mcam, REG_CSI2_DPHY6, mcam->dphy[2]);
mcam_reg_write(mcam, REG_CSI2_CTRL0,
mcam_reg_write(mcam, REG_CSI2_CTRL0, 0x0);
mcam_reg_write(mcam, REG_CSI2_DPHY3, 0x0);
mcam_reg_write(mcam, REG_CSI2_DPHY5, 0x0);
mcam_reg_write(mcam, REG_CSI2_DPHY6, 0x0);
mcam_reg_write(cam, REG_Y0BAR + frame * 4, y);
mcam_reg_write(cam, REG_U0BAR + frame * 4, u);
mcam_reg_write(cam, REG_V0BAR + frame * 4, v);
mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
mcam_reg_write(cam, REG_DESC_LEN_Y,
mcam_reg_write(cam, REG_DESC_LEN_U, 0);
mcam_reg_write(cam, REG_DESC_LEN_V, 0);
mcam_reg_write(cam, REG_IMGSIZE, imgsz_h | imgsz_w);
mcam_reg_write(cam, REG_IMGOFFSET, 0x0);
mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
mcam_reg_write(cam, REG_CLKCTRL, (mclk_src << 29) | mclk_div);
mcam_reg_write(cam, reg, v);