arch/x86/kernel/cpu/mce/amd.c

1170

err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));

arch/x86/kernel/cpu/mce/amd.c

552

addr = mca_msr_reg(bank, MCA_MISC);

arch/x86/kernel/cpu/mce/amd.c

891

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1317

mce_wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1378

m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS));

arch/x86/kernel/cpu/mce/core.c

1922

wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);

arch/x86/kernel/cpu/mce/core.c

1923

wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

1925

rdmsrq(mca_msr_reg(i, MCA_CTL), msrval);

arch/x86/kernel/cpu/mce/core.c

2423

wrmsrq(mca_msr_reg(i, MCA_CTL), 0);

arch/x86/kernel/cpu/mce/core.c

2779

wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl);

arch/x86/kernel/cpu/mce/core.c

361

if (msr == mca_msr_reg(bank, MCA_STATUS))

arch/x86/kernel/cpu/mce/core.c

363

if (msr == mca_msr_reg(bank, MCA_ADDR))

arch/x86/kernel/cpu/mce/core.c

365

if (msr == mca_msr_reg(bank, MCA_MISC))

arch/x86/kernel/cpu/mce/core.c

688

m->misc = mce_rdmsrq(mca_msr_reg(i, MCA_MISC));

arch/x86/kernel/cpu/mce/core.c

694

m->addr = mce_rdmsrq(mca_msr_reg(i, MCA_ADDR));

arch/x86/kernel/cpu/mce/core.c

798

mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);

arch/x86/kernel/cpu/mce/core.c

840

m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS));

arch/x86/kernel/cpu/mce/core.c

998

m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS));

arch/x86/kernel/cpu/mce/inject.c

751

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), status);

arch/x86/kernel/cpu/mce/inject.c

752

rdmsrq_safe(mca_msr_reg(bank, MCA_STATUS), &status);

arch/x86/kernel/cpu/mce/inject.c

753

wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), 0);