drivers/gpu/drm/amd/display/dc/basics/calcs_logger.h

382

for (i = 0; i < maximum_number_of_surfaces; i++) {

drivers/gpu/drm/amd/display/dc/basics/calcs_logger.h

536

for (i = 0; i < maximum_number_of_surfaces; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1001

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1087

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1105

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1126

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1132

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1145

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1176

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1203

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1288

for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1294

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1309

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

131

tiling_mode = kzalloc_objs(*tiling_mode, maximum_number_of_surfaces);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1328

for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

135

surface_type = kzalloc_objs(*surface_type, maximum_number_of_surfaces);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1374

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1389

for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1424

for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1433

for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1445

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1448

for (j = 0; j <= maximum_number_of_surfaces - 1; j++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1457

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1481

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1489

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1503

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1663

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1713

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1725

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1798

for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1820

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1837

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1854

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1861

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1896

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1933

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1943

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1971

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1995

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2012

for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

304

for (i = 4; i <= maximum_number_of_surfaces - 3; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

362

data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

363

data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

365

data->enable[maximum_number_of_surfaces - 2] = 1;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

366

data->enable[maximum_number_of_surfaces - 1] = 1;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

369

data->enable[maximum_number_of_surfaces - 2] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

370

data->enable[maximum_number_of_surfaces - 1] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

372

surface_type[maximum_number_of_surfaces - 2] = bw_def_display_write_back420_luma;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

373

surface_type[maximum_number_of_surfaces - 1] = bw_def_display_write_back420_chroma;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

374

data->lb_size_per_component[maximum_number_of_surfaces - 2] = dceip->underlay420_luma_lb_size_per_component;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

375

data->lb_size_per_component[maximum_number_of_surfaces - 1] = dceip->underlay420_chroma_lb_size_per_component;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

376

data->bytes_per_pixel[maximum_number_of_surfaces - 2] = 1;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

377

data->bytes_per_pixel[maximum_number_of_surfaces - 1] = 2;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

378

data->interlace_mode[maximum_number_of_surfaces - 2] = data->interlace_mode[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

379

data->interlace_mode[maximum_number_of_surfaces - 1] = data->interlace_mode[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

380

data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

381

data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

382

data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

383

data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

384

data->rotation_angle[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

385

data->rotation_angle[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

386

tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

387

tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

388

data->lb_bpc[maximum_number_of_surfaces - 2] = 8;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

389

data->lb_bpc[maximum_number_of_surfaces - 1] = 8;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

390

data->compression_rate[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

391

data->compression_rate[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

392

data->access_one_channel_only[maximum_number_of_surfaces - 2] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

393

data->access_one_channel_only[maximum_number_of_surfaces - 1] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

395

data->h_total[maximum_number_of_surfaces - 2] = data->h_total[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

396

data->h_total[maximum_number_of_surfaces - 1] = data->h_total[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

397

data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

398

data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

399

data->pixel_rate[maximum_number_of_surfaces - 2] = data->pixel_rate[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

400

data->pixel_rate[maximum_number_of_surfaces - 1] = data->pixel_rate[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

401

data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

402

data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

403

data->src_height[maximum_number_of_surfaces - 2] = data->src_height[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

404

data->src_height[maximum_number_of_surfaces - 1] = data->src_height[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

405

data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

406

data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

407

data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

408

data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

409

data->v_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

410

data->v_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

411

data->stereo_mode[maximum_number_of_surfaces - 2] = bw_def_mono;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

412

data->stereo_mode[maximum_number_of_surfaces - 1] = bw_def_mono;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

413

data->cursor_width_pixels[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

414

data->cursor_width_pixels[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

415

data->use_alpha[maximum_number_of_surfaces - 2] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

416

data->use_alpha[maximum_number_of_surfaces - 1] = 0;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

431

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

517

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

537

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

552

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

586

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

592

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

644

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

801

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

872

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

885

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

941

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

956

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

961

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

971

for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

363

bool fbc_en[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

364

bool lpt_en[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

365

bool displays_match_flag[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

366

bool use_alpha[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

367

bool orthogonal_rotation[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

368

bool enable[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

369

bool access_one_channel_only[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

370

bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

371

bool interlace_mode[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

372

bool display_pstate_change_enable[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

373

bool line_buffer_prefetch[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

374

uint32_t bytes_per_pixel[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

375

uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

376

uint32_t lb_bpc[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

377

uint32_t output_bpphdmi[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

378

uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

379

uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

380

uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

381

enum bw_defines stereo_mode[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

382

struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

383

struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

384

struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

385

struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

386

struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

387

struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

388

struct bw_fixed h_total[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

389

struct bw_fixed v_total[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

390

struct bw_fixed pixel_rate[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

391

struct bw_fixed src_width[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

392

struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

393

struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

394

struct bw_fixed src_height[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

395

struct bw_fixed scale_ratio[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

396

struct bw_fixed h_taps[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

397

struct bw_fixed v_taps[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

398

struct bw_fixed h_scale_ratio[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

399

struct bw_fixed v_scale_ratio[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

400

struct bw_fixed rotation_angle[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

401

struct bw_fixed compression_rate[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

402

struct bw_fixed hsr[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

403

struct bw_fixed vsr[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

404

struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

405

struct bw_fixed source_width_pixels[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

406

struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

407

struct bw_fixed display_bandwidth[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

408

struct bw_fixed request_bandwidth[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

409

struct bw_fixed bytes_per_request[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

410

struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

411

struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

412

struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

413

struct bw_fixed lb_partitions[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

414

struct bw_fixed lb_partitions_max[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

415

struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

416

struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

417

struct bw_fixed data_buffer_size[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

418

struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

419

struct bw_fixed urgent_watermark[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

420

struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

421

struct bw_fixed v_filter_init[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

422

struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

423

struct bw_fixed average_bandwidth[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

424

struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

425

struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

426

struct bw_fixed lb_size_per_component[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

427

struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

428

struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

429

struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

430

struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

431

struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

432

struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

433

struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

434

struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

435

struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

436

struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

437

struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

438

struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

439

struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

440

struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

441

struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

442

struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

443

struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

444

struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

445

struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

446

struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

447

struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

448

struct bw_fixed active_time[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

449

struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

450

struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

451

struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

455

struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8];

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

456

struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8];