CLK_PERI_UART2
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22),
GATE_MTK(CLK_PERI_UART2, "uart2", "uart_sel", &peri_cg_regs, 19, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),