CLK_PERI_UART0_PD
GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);