CLK_PERI_UART0
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
GATE_MTK(CLK_PERI_UART0, "uart0", "uart_sel", &peri_cg_regs, 17, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),