CLK_PERI_PWM7
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9),
GATE_MTK(CLK_PERI_PWM7, "pwm7", "axi_sel", &peri_cg_regs, 8, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),