CLK_PERI_PWM6
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8),
GATE_MTK(CLK_PERI_PWM6, "pwm6", "axi_sel", &peri_cg_regs, 7, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),