CLK_PERI_PWM5
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7),
GATE_MTK(CLK_PERI_PWM5, "pwm5", "axi_sel", &peri_cg_regs, 6, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),