CLK_PERI_PWM4
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6),
GATE_MTK(CLK_PERI_PWM4, "pwm4", "axi_sel", &peri_cg_regs, 5, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),