CLK_PERI_PWM3
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5),
GATE_MTK(CLK_PERI_PWM3, "pwm3", "axi_sel", &peri_cg_regs, 4, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),