CLK_PERI_PWM2
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4),
GATE_MTK(CLK_PERI_PWM2, "pwm2", "axi_sel", &peri_cg_regs, 3, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),