CLK_PERI_PWM1
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3),
GATE_MTK(CLK_PERI_PWM1, "pwm1", "axi_sel", &peri_cg_regs, 2, &mtk_clk_gate_ops_setclr),
GATE_PERI(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),