max310x_port_write
max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
max310x_port_write(port, MAX310X_MODE2_REG, val);
max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
max310x_port_write(port, MAX310X_FLOWLVL_REG,
max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
max310x_port_write(port, MAX310X_IRQEN_REG, 0);
max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
max310x_port_write(port, MAX310X_THR_REG, port->x_char);
max310x_port_write(port, MAX310X_LCR_REG, lcr);
max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);