mask_cache
ctrl->mask_cache &= ~BIT(d->hwirq);
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
ctrl->mask_cache = 0xffffffff;
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
u32 mask_cache;
pending &= ~ctrl->mask_cache;
ctrl->mask_cache |= BIT(d->hwirq);
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
gc->mask_cache = 0xffffffff;
pending &= ~gc->mask_cache;
irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
gc->mask_cache |= d->mask;
if ((mask & gc->mask_cache) == (mask & gc->wake_active))
((mask & gc->mask_cache) == (mask & gc->wake_active)))
if (mask & gc->mask_cache)
gc->mask_cache &= ~d->mask;
~cpu->mask_cache[idx];
intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
intc->cpus[cpu_idx]->mask_cache[word] |= mask;
was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
cpu = intc->cpus[idx] = kzalloc_flex(*cpu, mask_cache, n_words);
cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
u32 mask_cache[];
gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
pending = irq_reg_readl(gc, b->stat_offset[idx]) & gc->mask_cache &
irq_reg_writel(gc, gc->mask_cache | gc->wake_active, ct->regs.mask);
irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
*ct->mask_cache |= mask;
irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
gc->mask_cache = 0xffffffff;
pending &= ~idtpic->gc->mask_cache;
*ct->mask_cache |= mask;
*ct->mask_cache &= ~mask;
writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
gc->mask_cache = 0;
(handler->parent_int_map & gc->mask_cache &
*ct->mask_cache &= ~mask;
gc->mask_cache;
gc->mask_cache;
u32 mask_cache)
writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
stm32_chip_resume(chip_data, gc->mask_cache);
u32 mask_cache;
static void stm32mp_chip_resume(struct stm32mp_exti_chip_data *chip_data, u32 mask_cache)
writel_relaxed(mask_cache, base + bank->imr_ofst);
chip_data->mask_cache = stm32mp_exti_clr_bit(d, bank->imr_ofst);
chip_data->mask_cache = stm32mp_exti_set_bit(d, bank->imr_ofst);
stm32mp_chip_resume(chip_data, chip_data->mask_cache);
u32 mask_cache;
u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache;
u32 *mask_cache;
u32 mask_cache;
*ct->mask_cache |= mask;
*ct->mask_cache &= ~mask;
u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
ct[i].mask_cache = mskptr;
*ct->mask_cache &= ~mask;
*ct->mask_cache |= mask;
irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
*ct->mask_cache &= ~mask;
irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
static void __mask_cache_destroy(struct mask_cache *mc)
free_percpu(mc->mask_cache);
struct mask_cache *mc = container_of(rcu, struct mask_cache, rcu);
static struct mask_cache *tbl_mask_cache_alloc(u32 size)
struct mask_cache *new;
new->mask_cache = cache;
struct mask_cache *mc = rcu_dereference_ovsl(table->mask_cache);
struct mask_cache *new;
rcu_assign_pointer(table->mask_cache, new);
struct mask_cache *mc;
rcu_assign_pointer(table->mask_cache, mc);
struct mask_cache *mc = rcu_dereference_raw(table->mask_cache);
struct mask_cache *mc = rcu_dereference(tbl->mask_cache);
entries = this_cpu_ptr(mc->mask_cache);
struct mask_cache *mc = rcu_dereference_ovsl(table->mask_cache);
struct mask_cache_entry __percpu *mask_cache;
struct mask_cache __rcu *mask_cache;