mangle
if (act->mangle.htype == FLOW_ACT_MANGLE_HDR_TYPE_ETH)
switch (act->mangle.htype) {
void *dest = eth + act->mangle.offset;
const void *src = &act->mangle.val;
if (act->mangle.offset > 8)
if (act->mangle.mask == 0xffff) {
memcpy(dest, src, act->mangle.mask ? 2 : 4);
u32 val = be32_to_cpu((__force __be32)act->mangle.val);
switch (act->mangle.offset) {
if ((__force __be32)act->mangle.mask == ~cpu_to_be32(0xffff))
switch (act->mangle.offset) {
memcpy(dest, &act->mangle.val, sizeof(u32));
offset = act->mangle.offset;
htype = act->mangle.htype;
mask = ~act->mangle.mask;
val = act->mangle.val;
htype = act->mangle.htype;
mask = act->mangle.mask;
val = act->mangle.val;
offset = act->mangle.offset;
htype = act->mangle.htype;
mask = act->mangle.mask;
offset = act->mangle.offset;
u32 val = ntohl(act->mangle.val);
switch (act->mangle.offset) {
if (act->mangle.mask == ~htonl(0xffff))
switch (act->mangle.offset) {
memcpy(dest, &act->mangle.val, sizeof(u32));
if (act->mangle.htype == FLOW_ACT_MANGLE_HDR_TYPE_ETH)
switch (act->mangle.htype) {
void *dest = eth + act->mangle.offset;
const void *src = &act->mangle.val;
if (act->mangle.offset > 8)
if (act->mangle.mask == 0xffff) {
memcpy(dest, src, act->mangle.mask ? 2 : 4);
u8 htype = act->mangle.htype;
mask = act->mangle.mask;
val = act->mangle.val;
offset = act->mangle.offset;
.mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
.mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
.mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
.mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
offset = act->mangle.offset;
val = act->mangle.val;
switch (act->mangle.htype) {
u32 offset = act->mangle.offset, field;
switch (act->mangle.htype) {
MLX5_SET(set_action_in, modact, data, act->mangle.val);
htype = act->mangle.htype;
offset = act->mangle.offset;
mask = ~act->mangle.mask;
enum flow_action_mangle_base htype = act->mangle.htype;
__be32 be_mask = (__force __be32) act->mangle.mask;
__be32 be_val = (__force __be32) act->mangle.val;
u32 offset = act->mangle.offset;
mask = ~act->mangle.mask;
exact = act->mangle.val;
mask = (__force __be32)~act->mangle.mask;
exact = (__force __be32)act->mangle.val;
mask = (__force __be32)~act->mangle.mask;
exact = (__force __be32)act->mangle.val;
mask = ~act->mangle.mask;
exact = act->mangle.val;
htype = act->mangle.htype;
offset = act->mangle.offset;
switch (mangle_action->mangle.htype) {
mangle_action->mangle.val = (__force u32)cpu_to_be32(mangle_action->mangle.val);
mangle_action->mangle.mask = (__force u32)cpu_to_be32(mangle_action->mangle.mask);
if (mangle_action->mangle.offset == offsetof(struct tcphdr, source)) {
mangle_action->mangle.val =
(__force u32)cpu_to_be32(mangle_action->mangle.val << 16);
mangle_action->mangle.mask =
(__force u32)cpu_to_be32(mangle_action->mangle.mask << 16 | 0xFFFF);
if (mangle_action->mangle.offset == offsetof(struct tcphdr, dest)) {
mangle_action->mangle.offset = 0;
mangle_action->mangle.val =
(__force u32)cpu_to_be32(mangle_action->mangle.val);
mangle_action->mangle.mask =
(__force u32)cpu_to_be32(mangle_action->mangle.mask);
act->mangle.htype == htype) {
off = act->mangle.offset - offset;
msk = act->mangle.mask;
key = act->mangle.val;
switch (a_in->mangle.htype) {
switch (fa->mangle.htype) {
switch (fa->mangle.offset) {
if (fa->mangle.mask != ~EFX_TC_HDR_TYPE_TTL_MASK)
if ((fa->mangle.val & EFX_TC_HDR_TYPE_TTL_MASK) != U8_MAX)
switch (fa->mangle.offset) {
if (fa->mangle.mask != EFX_TC_HDR_TYPE_HLIMIT_MASK)
if ((fa->mangle.val >> 24) != U8_MAX)
fa->mangle.htype, fa->mangle.offset,
fa->mangle.val, fa->mangle.mask);
switch (fa->mangle.htype) {
switch (fa->mangle.offset) {
if (fa->mangle.mask) {
fa->mangle.mask);
mac32 = cpu_to_le32(fa->mangle.val);
if (fa->mangle.mask == 0xffff) {
mac16 = cpu_to_le16(fa->mangle.val >> 16);
} else if (fa->mangle.mask == 0xffff0000) {
mac16 = cpu_to_le16((u16)fa->mangle.val);
fa->mangle.mask);
if (fa->mangle.mask) {
fa->mangle.mask);
mac32 = cpu_to_le32(fa->mangle.val);
fa->mangle.offset, fa->mangle.val, fa->mangle.mask);
switch (fa->mangle.offset) {
if (fa->mangle.mask != ~EFX_TC_HDR_TYPE_TTL_MASK) {
fa->mangle.mask);
if ((fa->mangle.val & EFX_TC_HDR_TYPE_TTL_MASK) == tr_ttl) {
fa->mangle.offset);
switch (fa->mangle.offset) {
if (fa->mangle.mask != EFX_TC_HDR_TYPE_HLIMIT_MASK) {
fa->mangle.mask);
if ((fa->mangle.val >> 24) == tr_ttl) {
fa->mangle.htype);
switch (fa->mangle.htype) {
switch (fa->mangle.offset) {
if (fa->mangle.mask)
conn->nat_ip = htonl(fa->mangle.val);
switch (fa->mangle.offset) {
if (~fa->mangle.mask != 0xffff)
conn->l4_natport = htons(fa->mangle.val);
mangle(m, r->mnt_devname);
mangle(m, r->mnt_devname);
mangle(m, r->mnt_devname);
mangle(m, sb->s_type->name);
mangle(m, sb->s_subtype);
out[baselen + 1] = mangle(csum / MANGLE_BASE);
out[baselen + 2] = mangle(csum);
} mangle;
const struct arpt_mangle *mangle = par->targinfo;
if (mangle->flags & ARPT_MANGLE_SDEV) {
memcpy(arpptr, mangle->src_devaddr, hln);
if (mangle->flags & ARPT_MANGLE_SIP) {
memcpy(arpptr, &mangle->u_s.src_ip, pln);
if (mangle->flags & ARPT_MANGLE_TDEV) {
memcpy(arpptr, mangle->tgt_devaddr, hln);
if (mangle->flags & ARPT_MANGLE_TIP) {
memcpy(arpptr, &mangle->u_t.tgt_ip, pln);
return mangle->target;
const struct arpt_mangle *mangle = par->targinfo;
if (mangle->flags & ~ARPT_MANGLE_MASK ||
!(mangle->flags & ARPT_MANGLE_MASK))
if (mangle->target != NF_DROP && mangle->target != NF_ACCEPT &&
mangle->target != XT_CONTINUE)
entry->mangle.htype = htype;
entry->mangle.offset = offset;
memcpy(&entry->mangle.mask, mask, sizeof(u32));
memcpy(&entry->mangle.val, value, sizeof(u32));
entry->mangle.htype = htype;
entry->mangle.mask = ~mask;
entry->mangle.offset = offset;
entry->mangle.val = val;
entry->mangle.htype = tcf_pedit_htype(act, k);
entry->mangle.mask = tcf_pedit_mask(act, k);
entry->mangle.val = tcf_pedit_val(act, k);
entry->mangle.offset = tcf_pedit_offset(act, k);