malidp_read32
u32 tmp = malidp_read32(base, offset);
value = malidp_read32(reg, BLK_INFO);
max_default = malidp_read32(reg, BLK_MAX_LINE_SIZE);
layer_info = malidp_read32(reg, LAYER_INFO);
layer->line_sz = malidp_read32(reg, BLK_MAX_LINE_SIZE);
val[i] = malidp_read32(reg, addr);
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
status = malidp_read32(reg, BLK_STATUS) & 0x7FFFFFFF;
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
status = malidp_read32(reg, BLK_STATUS);
gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS);
raw_status = malidp_read32(d71->gcu_addr, BLK_IRQ_RAW_STATUS);
raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
status = malidp_read32(d71->gcu_addr, BLK_STATUS);
ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) == opmode),
status = malidp_read32(reg, BLK_STATUS);
ret = dp_wait_cond(!(malidp_read32(gcu, BLK_CONTROL) & GCU_CONTROL_SRST),
blk->block_info = malidp_read32(reg, BLK_BLOCK_INFO);
blk->pipeline_info = malidp_read32(reg, BLK_PIPELINE_INFO);
blk->input_ids[i] = malidp_read32(reg + i, BLK_VALID_INPUT_ID0);
blk->output_ids[i] = malidp_read32(reg + i, BLK_OUTPUT_ID0);
value = malidp_read32(d71->gcu_addr, GLB_CORE_INFO);
value = malidp_read32(d71->periph_addr, BLK_BLOCK_INFO);
value = malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);
value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID0);
value = malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID1);
ret = dp_wait_cond(has_bits(check_bits, malidp_read32(reg, BLK_STATUS)),
ret = dp_wait_cond(((malidp_read32(reg, BLK_STATUS) & check_bits) == 0),
chip->core_id = malidp_read32(reg_base, GLB_CORE_ID);
chip->arch_id = malidp_read32(reg_base, GLB_ARCH_ID);
chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO);
tbu_status = malidp_read32(reg, LPU_TBU_STATUS);