mace_write
mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
mace_write(lp, ioaddr, MACE_MACCC,
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
mace_write(lp, ioaddr, MACE_MACCC,
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
mace_write(lp, ioaddr, MACE_BIUCC, 1);
mace_write(lp, ioaddr, MACE_BIUCC, 0);
mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
mace_write(lp, ioaddr, MACE_MACCC, 0x00);
mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);