m_can_write
m_can_write(cdev, M_CAN_IR, IR_MRAF);
m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
m_can_write(cdev, M_CAN_IR, ir);
m_can_write(cdev, M_CAN_NBTP, reg_btp);
m_can_write(cdev, M_CAN_TDCR,
m_can_write(cdev, M_CAN_DBTP, reg_btp);
m_can_write(cdev, M_CAN_RXESC,
m_can_write(cdev, M_CAN_GFC, 0x0);
m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |
m_can_write(cdev, M_CAN_TXBC,
m_can_write(cdev, M_CAN_TXESC,
m_can_write(cdev, M_CAN_TXEFC,
m_can_write(cdev, M_CAN_TXEFC,
m_can_write(cdev, M_CAN_RXF0C,
m_can_write(cdev, M_CAN_RXF1C,
m_can_write(cdev, M_CAN_CCCR, cccr);
m_can_write(cdev, M_CAN_TEST, test);
m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
m_can_write(cdev, M_CAN_TSCC,
m_can_write(cdev, M_CAN_CCCR, cccr);
m_can_write(cdev, M_CAN_TXBTIE, 0x1);
m_can_write(cdev, M_CAN_TXBAR, 0x1);
m_can_write(cdev, M_CAN_TXBAR, BIT(putidx));
m_can_write(cdev, M_CAN_TXBAR, cdev->tx_peripheral_submit);
m_can_write(cdev, M_CAN_IE, IR_RF0N);
m_can_write(cdev, M_CAN_IE, cdev->active_interrupts);
m_can_write(cdev, M_CAN_CCCR, val_after);
m_can_write(cdev, M_CAN_IE, interrupts);
m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
m_can_write(cdev, M_CAN_ILE, 0x0);
m_can_write(cdev, M_CAN_RXF0A, ack_fgi);