drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

235

lane_count = dp->link_train.lane_count;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

237

dp->link_train.lt_state = CLOCK_RECOVERY;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

238

dp->link_train.eq_loop = 0;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

241

dp->link_train.cr_loop[lane] = 0;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

244

analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

255

analogix_dp_set_lane_count(dp, dp->link_train.lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

258

buf[0] = dp->link_train.link_rate;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

259

buf[1] = dp->link_train.lane_count;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

272

dp->link_train.training_lane[lane] =

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

288

dp->link_train.training_lane, lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

300

dp->link_train.lt_state = FAILED;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

309

lane_count = dp->link_train.lane_count;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

323

dp->link_train.training_lane[lane] = training_lane;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

335

lane_count = dp->link_train.lane_count;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

352

dp->link_train.lt_state = EQUALIZER_TRAINING;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

366

dp->link_train.cr_loop[lane]++;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

368

if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

372

dp->link_train.cr_loop[lane],

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

383

dp->link_train.training_lane, lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

398

lane_count = dp->link_train.lane_count;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

419

dp->link_train.link_rate = reg;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

421

dp->link_train.link_rate);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

424

dp->link_train.lane_count = reg;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

426

dp->link_train.lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

428

dp->link_train.lt_state = FINISHED;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

434

dp->link_train.eq_loop++;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

436

if (dp->link_train.eq_loop > MAX_EQ_LOOP) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

445

dp->link_train.training_lane, lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

487

analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

488

analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

490

if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

491

(dp->link_train.link_rate != DP_LINK_BW_2_7) &&

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

492

(dp->link_train.link_rate != DP_LINK_BW_5_4)) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

494

dp->link_train.link_rate);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

495

dp->link_train.link_rate = DP_LINK_BW_1_62;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

498

if (dp->link_train.lane_count == 0) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

500

dp->link_train.lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

501

dp->link_train.lane_count = (u8)LANE_COUNT1;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

505

if (dp->link_train.lane_count > max_lanes)

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

506

dp->link_train.lane_count = max_lanes;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

507

if (dp->link_train.link_rate > max_rate)

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

508

dp->link_train.link_rate = max_rate;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

513

dp->link_train.lt_state = START;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

517

switch (dp->link_train.lt_state) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

551

analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

563

analogix_dp_set_lane_count(dp, dp->link_train.lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

590

if (!drm_dp_clock_recovery_ok(link_status, dp->link_train.lane_count)) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

596

if (!drm_dp_channel_eq_ok(link_status, dp->link_train.lane_count)) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.h

164

struct link_train link_train;

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

527

drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

556

phy_cfg.dp.lanes = dp->link_train.lane_count;

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

579

for (lane = 0; lane < dp->link_train.lane_count; lane++)

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

580

writel(dp->link_train.training_lane[lane],

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

586

for (lane = 0; lane < dp->link_train.lane_count; lane++) {

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

587

u8 training_lane = dp->link_train.training_lane[lane];