m88rs2000_writereg
ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));
ret |= m88rs2000_writereg(state, 0x9d, reg);
ret = m88rs2000_writereg(state, 0x93, b[2]);
ret |= m88rs2000_writereg(state, 0x94, b[1]);
ret |= m88rs2000_writereg(state, 0x95, b[0]);
ret |= m88rs2000_writereg(state, 0xa0, 0x20);
ret |= m88rs2000_writereg(state, 0xa0, 0x60);
ret |= m88rs2000_writereg(state, 0xa1, 0xe0);
ret |= m88rs2000_writereg(state, 0xa3, 0x20);
ret |= m88rs2000_writereg(state, 0xa3, 0x98);
ret |= m88rs2000_writereg(state, 0xa3, 0x90);
m88rs2000_writereg(state, 0x9a, 0x30);
m88rs2000_writereg(state, 0xb2, reg);
m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
m88rs2000_writereg(state, 0xb1, reg);
m88rs2000_writereg(state, 0xb1, reg);
m88rs2000_writereg(state, 0xb2, reg);
m88rs2000_writereg(state, 0x9a, 0xb0);
m88rs2000_writereg(state, 0x9a, 0x30);
m88rs2000_writereg(state, 0xb2, reg1);
m88rs2000_writereg(state, 0xb1, reg0);
m88rs2000_writereg(state, 0x9a, 0xb0);
m88rs2000_writereg(state, 0x9a, 0x30);
m88rs2000_writereg(state, 0xb2, reg1);
m88rs2000_writereg(state, 0xb1, reg0);
m88rs2000_writereg(state, 0x9a, 0xb0);
ret = m88rs2000_writereg(state, tab[i].reg,
m88rs2000_writereg(state, 0xb2, data);
m88rs2000_writereg(state, 0x9a, 0x30);
m88rs2000_writereg(state, 0x9a, 0xb0);
m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
m88rs2000_writereg(state, 0x9a, 0xb0);
m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
m88rs2000_writereg(state, 0xd8, tmp | 0x20);
m88rs2000_writereg(state, 0xd8, tmp | 0x20);
ret = m88rs2000_writereg(state, 0x70, reg | fec_set);
ret |= m88rs2000_writereg(state, 0x76, 0x8);
m88rs2000_writereg(state, 0x9a, 0x30);
m88rs2000_writereg(state, 0x9a, 0xb0);
ret = m88rs2000_writereg(state, 0x86, 0xc2);
ret = m88rs2000_writereg(state, 0x86, 0xc6);
ret = m88rs2000_writereg(state, 0xf1, 0xa4);
ret = m88rs2000_writereg(state, 0xf1, 0xbf);
ret |= m88rs2000_writereg(state, 0x85, 0x1);
ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
ret |= m88rs2000_writereg(state, 0x90, 0xf1);
ret |= m88rs2000_writereg(state, 0x91, 0x08);
m88rs2000_writereg(state, 0x70, reg);
m88rs2000_writereg(state, 0x81, 0x84);
m88rs2000_writereg(state, 0x81, 0x81);