drivers/clk/clk-mux.c

111

if (mux->flags & CLK_MUX_HIWORD_MASK) {

drivers/clk/clk-mux.c

162

if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {

drivers/clk/hisilicon/clk-hi3620.c

100

{ HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

101

{ HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

102

{ HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

103

{ HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

104

{ HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

105

{ HI3620_PWM1_MUX, "pwm1_mux", pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), CLK_SET_RATE_PARENT, 0x104, 11, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

106

{ HI3620_SD_MUX, "sd_mux", sd_mux_p, ARRAY_SIZE(sd_mux_p), CLK_SET_RATE_PARENT, 0x108, 4, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

107

{ HI3620_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p), CLK_SET_RATE_PARENT, 0x108, 9, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

108

{ HI3620_MMC1_MUX2, "mmc1_mux2", mmc1_mux2_p, ARRAY_SIZE(mmc1_mux2_p), CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

109

{ HI3620_G2D_MUX, "g2d_mux", g2d_mux_p, ARRAY_SIZE(g2d_mux_p), CLK_SET_RATE_PARENT, 0x10c, 5, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

110

{ HI3620_VENC_MUX, "venc_mux", venc_mux_p, ARRAY_SIZE(venc_mux_p), CLK_SET_RATE_PARENT, 0x10c, 11, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

111

{ HI3620_VDEC_MUX, "vdec_mux", vdec_mux_p, ARRAY_SIZE(vdec_mux_p), CLK_SET_RATE_PARENT, 0x110, 5, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

112

{ HI3620_VPP_MUX, "vpp_mux", vpp_mux_p, ARRAY_SIZE(vpp_mux_p), CLK_SET_RATE_PARENT, 0x110, 11, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

113

{ HI3620_EDC0_MUX, "edc0_mux", edc0_mux_p, ARRAY_SIZE(edc0_mux_p), CLK_SET_RATE_PARENT, 0x114, 6, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

114

{ HI3620_LDI0_MUX, "ldi0_mux", ldi0_mux_p, ARRAY_SIZE(ldi0_mux_p), CLK_SET_RATE_PARENT, 0x114, 13, 2, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

115

{ HI3620_EDC1_MUX, "edc1_mux", edc1_mux_p, ARRAY_SIZE(edc1_mux_p), CLK_SET_RATE_PARENT, 0x118, 6, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

116

{ HI3620_LDI1_MUX, "ldi1_mux", ldi1_mux_p, ARRAY_SIZE(ldi1_mux_p), CLK_SET_RATE_PARENT, 0x118, 14, 2, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

117

{ HI3620_RCLK_HSIC, "rclk_hsic", rclk_hsic_p, ARRAY_SIZE(rclk_hsic_p), CLK_SET_RATE_PARENT, 0x130, 2, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

118

{ HI3620_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p), CLK_SET_RATE_PARENT, 0x140, 4, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

119

{ HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

95

{ HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

96

{ HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

97

{ HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

98

{ HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3620.c

99

{ HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

271

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

274

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

277

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

280

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

283

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

286

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

289

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

292

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

295

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

298

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

301

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

304

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

307

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

310

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

313

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

316

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

319

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

322

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

325

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

328

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

331

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

441

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3660.c

444

CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

420

0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

423

0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

426

0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

429

0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

432

0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

435

0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

438

0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

441

0x100, 0, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

444

0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

447

0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

450

0xAC, 2, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

453

0xAC, 13, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

456

0xAC, 8, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

459

0xb4, 5, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

462

0x100, 6, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

465

0xC8, 8, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

468

0xC8, 4, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

471

0x108, 3, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

474

0x10C, 13, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

477

0x10C, 10, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

480

0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

483

0xc8, 12, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

636

0x274, 8, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

639

0x254, 12, 2, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

642

0x254, 14, 2, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

645

CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

648

0x268, 9, 2, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

785

0x74, 6, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

788

0x68, 6, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

791

0x60, 6, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

794

0x64, 6, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi3670.c

797

0x88, 0, 4, CLK_MUX_HIWORD_MASK, },

drivers/clk/hisilicon/clk-hi6220.c

153

{ HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

154

{ HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

155

{ HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

156

{ HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

157

{ HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

158

{ HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

159

{ HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

160

{ HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

161

{ HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

162

{ HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/hisilicon/clk-hi6220.c

163

{ HI6220_MMC2_MUX1, "mmc2_mux1", mmc2_mux1_p, ARRAY_SIZE(mmc2_mux1_p), CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,},

drivers/clk/renesas/r9a08g045-cpg.c

60

.mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \

drivers/clk/renesas/rzg2l-cpg.h

181

.mux_flags = CLK_MUX_HIWORD_MASK)

drivers/clk/renesas/rzv2h-cpg.h

235

.mux_flags = CLK_MUX_HIWORD_MASK)

drivers/clk/rockchip/clk-muxgrf.c

44

if (mux->flags & CLK_MUX_HIWORD_MASK)

drivers/clk/rockchip/clk-pll.c

1101

pll_mux->flags |= CLK_MUX_HIWORD_MASK;

drivers/clk/rockchip/clk-px30.c

204

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3036.c

146

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3128.c

169

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3188.c

237

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3228.c

179

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3288.c

245

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3308.c

194

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3328.c

232

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3368.c

151

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3399.c

240

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3506.c

150

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3528.c

203

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3562.c

146

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3568.c

350

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3576.c

276

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3588.c

520

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rv1108.c

162

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rv1126.c

211

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rv1126b.c

175

#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/ti/mux.c

73

if (mux->flags & CLK_MUX_HIWORD_MASK) {

drivers/clk/zynqmp/clk-mux-zynqmp.c

109

ccf_flag |= CLK_MUX_HIWORD_MASK;