drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

234

dp->link_train.lt_state = CLOCK_RECOVERY;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

360

dp->link_train.lt_state = FAILED;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

412

dp->link_train.lt_state = EQUALIZER_TRAINING;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

501

dp->link_train.lt_state = FINISHED;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

586

dp->link_train.lt_state = START;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

590

switch (dp->link_train.lt_state) {

drivers/gpu/drm/bridge/analogix/analogix_dp_core.h

150

enum link_training_state lt_state;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1536

intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1541

lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >> 24); \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1542

lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >> 16); \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1543

lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8); \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1544

lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF)); \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1548

lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1549

lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1650

lt_state->config[0] = 0x84;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1651

lt_state->config[1] = 0x2d;

drivers/gpu/drm/i915/display/intel_lt_phy.c

1686

(lt_state->data[i][3]) | \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1687

(lt_state->data[i][2] << 8) | \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1688

(lt_state->data[i][1] << 16) | \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1689

(lt_state->data[i][0] << 24) \

drivers/gpu/drm/i915/display/intel_lt_phy.c

1693

const struct intel_lt_phy_pll_state *lt_state =

drivers/gpu/drm/i915/display/intel_lt_phy.c

1757

const struct intel_lt_phy_pll_state *lt_state =

drivers/gpu/drm/i915/display/intel_lt_phy.c

1762

lt_state->config[0]);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1771

lt_state->config[0]);

drivers/gpu/drm/i915/display/intel_lt_phy.h

39

intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

132

nvkm_dp_train_drive(struct lt_state *lt, bool pc)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

203

nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

229

nvkm_dp_train_eq(struct lt_state *lt)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

276

nvkm_dp_train_cr(struct lt_state *lt)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

316

struct lt_state lt = {

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

475

struct lt_state lt = {

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c

92

nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay)