lt_err
lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",
lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");
lt_err(intel_dp, dp_phy, "Failed to get link status\n");
lt_err(intel_dp, dp_phy, "Failed to update link training\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
lt_err(intel_dp, DP_PHY_DPRX,
lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");
lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n");
lt_err(intel_dp, dp_phy, "Failed to enable link training\n");
lt_err(intel_dp, dp_phy, "Failed to get link status\n");
lt_err(intel_dp, dp_phy, "Failed to update link training\n");