drivers/gpu/drm/sprd/sprd_dpu.c

344

layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);

drivers/gpu/drm/sprd/sprd_dpu.c

346

layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);

drivers/gpu/drm/sprd/sprd_dpu.c

348

layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);

drivers/gpu/drm/sprd/sprd_dpu.c

359

layer_reg_wr(ctx, REG_LAY_POS, offset, index);

drivers/gpu/drm/sprd/sprd_dpu.c

360

layer_reg_wr(ctx, REG_LAY_SIZE, size, index);

drivers/gpu/drm/sprd/sprd_dpu.c

361

layer_reg_wr(ctx, REG_LAY_CROP_START,

drivers/gpu/drm/sprd/sprd_dpu.c

363

layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);

drivers/gpu/drm/sprd/sprd_dpu.c

364

layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);

drivers/gpu/drm/sprd/sprd_dpu.c

370

layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |

drivers/gpu/drm/sprd/sprd_dpu.c

546

layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);