lan78xx_write_reg
ret = lan78xx_write_reg(dev, HW_CFG, val);
ret = lan78xx_write_reg(dev, E2P_CMD, val);
int rc = lan78xx_write_reg(dev, HW_CFG, saved);
ret = lan78xx_write_reg(dev, HW_CFG, val);
ret = lan78xx_write_reg(dev, E2P_CMD, val);
ret = lan78xx_write_reg(dev, E2P_DATA, val);
ret = lan78xx_write_reg(dev, E2P_CMD, val);
int rc = lan78xx_write_reg(dev, HW_CFG, saved);
ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
ret = lan78xx_write_reg(dev, OTP_ADDR1,
ret = lan78xx_write_reg(dev, OTP_ADDR2,
ret = lan78xx_write_reg(dev, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_);
ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
ret = lan78xx_write_reg(dev, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
ret = lan78xx_write_reg(dev, OTP_ADDR1,
ret = lan78xx_write_reg(dev, OTP_ADDR2,
ret = lan78xx_write_reg(dev, OTP_PRGM_DATA, data[i]);
ret = lan78xx_write_reg(dev, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
ret = lan78xx_write_reg(dev, DP_ADDR, addr + i);
ret = lan78xx_write_reg(dev, DP_DATA, buf[i]);
ret = lan78xx_write_reg(dev, DP_CMD, DP_CMD_WRITE_);
ret = lan78xx_write_reg(dev, MAF_HI(i), 0);
ret = lan78xx_write_reg(dev, MAF_LO(i),
ret = lan78xx_write_reg(dev, MAF_HI(i),
ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
ret = lan78xx_write_reg(dev, MAC_CR, val);
return lan78xx_write_reg(dev, INT_STS, INT_STS_PHY_INT_);
ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
ret = lan78xx_write_reg(dev, MII_ACC, addr);
ret = lan78xx_write_reg(dev, MII_DATA, val);
ret = lan78xx_write_reg(dev, MII_ACC, addr);
ret = lan78xx_write_reg(dev, INT_EP_CTL, data->irqenable);
ret = lan78xx_write_reg(dev, FCT_FLOW, fct_flow);
return lan78xx_write_reg(dev, FLOW, flow);
ret = lan78xx_write_reg(dev, EEE_TX_LPI_REQ_DLY, timer);
ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
ret = lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
ret = lan78xx_write_reg(dev, MAC_RGMII_ID, 0);
return lan78xx_write_reg(dev, HW_CFG, reg);
ret = lan78xx_write_reg(dev, MAC_RX, buf);
ret = lan78xx_write_reg(dev, MAC_RX, buf);
ret = lan78xx_write_reg(dev, MAC_RX, buf);
ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
return lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
return lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
ret = lan78xx_write_reg(dev, LTM_BELT_IDLE0, regs[0]);
ret = lan78xx_write_reg(dev, LTM_BELT_IDLE1, regs[1]);
ret = lan78xx_write_reg(dev, LTM_BELT_ACT0, regs[2]);
ret = lan78xx_write_reg(dev, LTM_BELT_ACT1, regs[3]);
ret = lan78xx_write_reg(dev, LTM_INACTIVE0, regs[4]);
ret = lan78xx_write_reg(dev, LTM_INACTIVE1, regs[5]);
ret = lan78xx_write_reg(dev, HW_CFG, buf);
ret = lan78xx_write_reg(dev, USB_CFG0, buf);
ret = lan78xx_write_reg(dev, BURST_CAP, dev->burst_cap);
ret = lan78xx_write_reg(dev, BULK_IN_DLY, dev->bulk_in_delay);
ret = lan78xx_write_reg(dev, HW_CFG, buf);
ret = lan78xx_write_reg(dev, USB_CFG0, buf);
ret = lan78xx_write_reg(dev, FCT_RX_FIFO_END, buf);
ret = lan78xx_write_reg(dev, FCT_TX_FIFO_END, buf);
ret = lan78xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
ret = lan78xx_write_reg(dev, FLOW, 0);
ret = lan78xx_write_reg(dev, FCT_FLOW, 0);
ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
ret = lan78xx_write_reg(dev, PMT_CTL, buf);
ret = lan78xx_write_reg(dev, MAC_CR, buf);
ret = lan78xx_write_reg(dev, WUCSR, 0);
ret = lan78xx_write_reg(dev, WUCSR2, 0);
ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
ret = lan78xx_write_reg(dev, WUCSR, buf);
ret = lan78xx_write_reg(dev, PMT_CTL, buf);
ret = lan78xx_write_reg(dev, PMT_CTL, buf);
ret = lan78xx_write_reg(dev, WUCSR, 0);
ret = lan78xx_write_reg(dev, WUCSR2, 0);
ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
ret = lan78xx_write_reg(dev, WUF_CFG(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 7);
ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 3);
ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 0x3000);
ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
ret = lan78xx_write_reg(dev, WUCSR, temp_wucsr);
ret = lan78xx_write_reg(dev, PMT_CTL, temp_pmt_ctl);
ret = lan78xx_write_reg(dev, PMT_CTL, buf);
ret = lan78xx_write_reg(dev, WUCSR, 0);
ret = lan78xx_write_reg(dev, WUCSR2, 0);
ret = lan78xx_write_reg(dev, PMT_CTL, buf);
ret = lan78xx_write_reg(dev, PMT_CTL, buf);
ret = lan78xx_write_reg(dev, WUCSR2, 0);
ret = lan78xx_write_reg(dev, WUCSR, 0);
ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
ret = lan78xx_write_reg(dev, WUCSR2, WUCSR2_NS_RCD_ |
ret = lan78xx_write_reg(dev, WUCSR, WUCSR_EEE_TX_WAKE_ |
return lan78xx_write_reg(dev, reg, buf);
ret = lan78xx_write_reg(dev, reg, buf);