arch/loongarch/include/asm/cacheflush.h

35

void local_flush_icache_range(unsigned long start, unsigned long end);

arch/loongarch/include/asm/cacheflush.h

37

#define flush_icache_range local_flush_icache_range

arch/loongarch/include/asm/cacheflush.h

38

#define flush_icache_user_range local_flush_icache_range

arch/loongarch/kernel/traps.c

1175

local_flush_icache_range(eentry + offset, eentry + offset + size);

arch/loongarch/kernel/traps.c

1210

local_flush_icache_range(eentry, eentry + 0x400);

arch/loongarch/mm/cache.c

42

EXPORT_SYMBOL(local_flush_icache_range);

arch/loongarch/mm/tlb.c

281

local_flush_icache_range(tlbrentry, tlbrentry + 0x80);

arch/loongarch/mm/tlb.c

306

local_flush_icache_range((unsigned long)addr, (unsigned long)addr + vec_sz);

arch/mips/include/asm/cacheflush.h

89

extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);

arch/mips/kernel/machine_kexec.c

164

local_flush_icache_range((unsigned long)relocated_kexec_smp_wait,

arch/mips/kernel/machine_kexec.c

202

local_flush_icache_range(reboot_code_buffer,

arch/mips/kernel/pm-cps.c

624

local_flush_icache_range((unsigned long)buf, (unsigned long)p);

arch/mips/kernel/smp-bmips.c

383

local_flush_icache_range(0, ~0);

arch/mips/kernel/smp-bmips.c

471

local_flush_icache_range(dst, dst + (end - start));

arch/mips/kernel/traps.c

2054

local_flush_icache_range(ebase + 0x200, (unsigned long)buf);

arch/mips/kernel/traps.c

2124

local_flush_icache_range((unsigned long)b,

arch/mips/kernel/traps.c

2289

local_flush_icache_range(ebase + offset, ebase + offset + size);

arch/mips/kernel/traps.c

2499

local_flush_icache_range(ebase, ebase + vec_size);

arch/mips/kvm/vz.c

1123

local_flush_icache_range(0, 0);

arch/mips/mm/c-octeon.c

280

local_flush_icache_range = local_octeon_flush_icache_range;

arch/mips/mm/c-r3k.c

295

local_flush_icache_range = r3k_flush_icache_range;

arch/mips/mm/c-r4k.c

1747

local_flush_icache_range = local_r4k_flush_icache_range;

arch/mips/mm/c-r4k.c

1789

local_flush_icache_range = (void *)b5k_instruction_hazard;

arch/mips/mm/cache.c

39

void (*local_flush_icache_range)(unsigned long start, unsigned long end);

arch/mips/mm/cache.c

40

EXPORT_SYMBOL_GPL(local_flush_icache_range);

arch/mips/mm/tlbex.c

1422

local_flush_icache_range(ebase, ebase + 0x100);

arch/mips/mm/tlbex.c

1528

local_flush_icache_range(ebase + 0x80, ebase + 0x100);

arch/mips/mm/tlbex.c

2351

local_flush_icache_range((unsigned long)handle_tlbl,

arch/mips/mm/tlbex.c

2353

local_flush_icache_range((unsigned long)handle_tlbs,

arch/mips/mm/tlbex.c

2355

local_flush_icache_range((unsigned long)handle_tlbm,

arch/mips/mm/tlbex.c

2357

local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,

arch/mips/mm/tlbex.c

422

local_flush_icache_range(ebase, ebase + 0x80);

arch/riscv/kernel/patch.c

152

local_flush_icache_range((unsigned long)waddr,

arch/riscv/kernel/patch.c

98

local_flush_icache_range((unsigned long)waddr,

arch/sh/include/asm/cacheflush.h

27

extern void (*local_flush_icache_range)(void *args);

arch/sh/mm/cache-j2.c

59

local_flush_icache_range = j2_flush_icache;

arch/sh/mm/cache-sh2a.c

183

local_flush_icache_range = sh2a_flush_icache_range;

arch/sh/mm/cache-sh4.c

390

local_flush_icache_range = sh4_flush_icache_range;

arch/sh/mm/cache-sh7705.c

192

local_flush_icache_range = sh7705_flush_icache_range;

arch/sh/mm/cache.c

239

cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);

arch/sh/mm/cache.c

24

void (*local_flush_icache_range)(void *args) = cache_noop;

arch/xtensa/include/asm/cacheflush.h

110

#define flush_icache_range local_flush_icache_range

arch/xtensa/include/asm/cacheflush.h

143

#define flush_icache_range local_flush_icache_range

arch/xtensa/kernel/jump_label.c

36

local_flush_icache_range(addr, addr + sz);

arch/xtensa/kernel/smp.c

592

local_flush_icache_range(fd->addr1, fd->addr2);