lio_pci_writeq
lio_pci_writeq(oct, 1, CN23XX_RST_SOFT_RST);
lio_pci_writeq(oct, (READ_ONCE(bar1) & 0xFFFFFFFEULL),
lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK),
lio_pci_writeq(oct, mask,
lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));
lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_BIST);
lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_RST);
lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL),
lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK),
lio_pci_writeq(oct, mask, CN6XXX_BAR1_REG(idx, oct->pcie_port));
lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));
lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL);
lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i));
lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i));
lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL);
lio_pci_writeq(oct, comp, CN6XXX_MIO_PTP_CLOCK_COMP);
lio_pci_writeq(oct, ns, CN6XXX_MIO_PTP_CLOCK_HI);
lio_pci_writeq(oct, clock_comp, CN6XXX_MIO_PTP_CLOCK_COMP);
lio_pci_writeq(oct, cfg | 0x01, CN6XXX_MIO_PTP_CLOCK_CFG);
EXPORT_SYMBOL_GPL(lio_pci_writeq);
void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr);