lio_pci_readq
return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50);
lio_pci_readq(oct, CN23XX_RST_SOFT_RST);
reg_adr = lio_pci_readq(
reg_adr = lio_pci_readq(
WRITE_ONCE(bar1, lio_pci_readq(
return (u32)lio_pci_readq(
r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));
return ((lio_pci_readq(oct, CN6XXX_MIO_RST_BOOT) >> 24) & 0x3f) * 50;
lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST);
bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));
bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));
bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));
return (u32)lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port));
r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port));
u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG);
lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL));
lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i)));
lio_pci_readq(oct, CN6XXX_DPI_CTL));
reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port));
comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP);
ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI);
cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG);
EXPORT_SYMBOL_GPL(lio_pci_readq);
lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL);
lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL);
u64 lio_pci_readq(struct octeon_device *oct, u64 addr);