lgdt3305_write_reg
ret = lgdt3305_write_reg(state, 0x0808, 0x80);
ret = lgdt3305_write_reg(state, 0x0808, 0x00);
ret = lgdt3305_write_reg(state, reg, val);
ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
lgdt3305_write_reg(state, 0x030d, 0x00);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
lgdt3305_write_reg(state, 0x030d, 0x14);
ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);