arch/powerpc/math-emu/math.c

241

case LFS: func = lfs; type = D; break;

arch/powerpc/math-emu/math.c

242

case LFSU: func = lfs; type = DU; break;

arch/powerpc/math-emu/math.c

252

case LFSX: func = lfs; type = XE; break;

arch/powerpc/math-emu/math.c

253

case LFSUX: func = lfs; type = XEU; break;

arch/powerpc/math-emu/math.c

63

FLOATFUNC(lfs);

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

103

ret = otx2_cpt_lmtst_tbl_setup_msg(&cptpf->lfs);

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

107

cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

123

size = cptvf->lfs.lfs_num * LMTLINE_SIZE + LMTLINE_ALIGN;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

124

ret = cn10k_cpt_lmtst_alloc(pdev, &cptvf->lfs, size);

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

131

ret = otx2_cpt_lmtst_tbl_setup_msg(&cptvf->lfs);

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

135

cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

200

struct otx2_cptlfs_info *lfs = &cptvf->lfs;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

207

otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, lfs->lf[0].slot,

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

211

otx2_cpt_read64(lfs->reg_base, lfs->blkaddr, lfs->lf[0].slot,

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

219

cptvf->lfs.ops = &cn10k_hw_ops;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

221

cptvf->lfs.ops = &otx2_hw_ops;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

31

void *lmtline = lf->lfs->lmt_info.base + (lf->slot * LMTLINE_SIZE);

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

49

void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

51

struct otx2_lmt_info *lmt_info = &lfs->lmt_info;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

64

struct otx2_cptlfs_info *lfs, u32 size)

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

66

struct otx2_lmt_info *lmt_info = &lfs->lmt_info;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

90

cptpf->lfs.ops = &otx2_hw_ops;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

94

cptpf->lfs.ops = &cn10k_hw_ops;

drivers/crypto/marvell/octeontx2/cn10k_cpt.c

96

ret = cn10k_cpt_lmtst_alloc(pdev, &cptpf->lfs, size);

drivers/crypto/marvell/octeontx2/cn10k_cpt.h

53

void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

206

int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

207

int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

208

int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

210

int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot);

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

211

int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

126

int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

128

struct otx2_mbox *mbox = lfs->mbox;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

136

dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

143

req->cptlfs = lfs->lfs_num;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

144

req->cpt_blkaddr = lfs->blkaddr;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

146

ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

150

if (!lfs->are_lfs_attached)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

156

int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

158

struct otx2_mbox *mbox = lfs->mbox;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

166

dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

174

ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

178

if (lfs->are_lfs_attached)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

185

int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

187

struct otx2_mbox *mbox = lfs->mbox;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

188

struct pci_dev *pdev = lfs->pdev;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

206

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

207

if (lfs->lf[i].msix_offset == MSIX_VECTOR_INVALID) {

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

210

lfs->lf[i].msix_offset, i);

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

233

int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

235

struct otx2_mbox *mbox = lfs->mbox;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

236

struct pci_dev *pdev = lfs->pdev;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

259

int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

261

struct otx2_mbox *mbox = lfs->mbox;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

262

struct pci_dev *pdev = lfs->pdev;

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

278

req->lmt_iova = lfs->lmt_info.iova;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

102

ret = cptlf_set_eng_grps_mask(&lfs->lf[slot], eng_grp_mask);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

109

static int cptlf_set_ctx_ilen(struct otx2_cptlfs_info *lfs, int ctx_ilen)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

115

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

116

lf = &lfs->lf[slot];

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

118

ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

120

&lf_ctrl.u, lfs->blkaddr);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

126

ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

128

lf_ctrl.u, lfs->blkaddr);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

135

static void cptlf_hw_init(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

138

otx2_cptlf_disable_iqueues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

141

otx2_cptlf_set_iqueues_base_addr(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

144

otx2_cptlf_set_iqueues_size(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

147

cptlf_set_done_time_wait(lfs, CPT_TIMER_HOLD);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

150

cptlf_set_done_num_wait(lfs, CPT_COUNT_HOLD);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

153

otx2_cptlf_enable_iqueues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

156

static void cptlf_hw_cleanup(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

159

otx2_cptlf_disable_iqueues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

16

done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

162

static void cptlf_set_misc_intrs(struct otx2_cptlfs_info *lfs, u8 enable)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

175

for (slot = 0; slot < lfs->lfs_num; slot++)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

176

otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot, reg,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

180

static void cptlf_set_done_intrs(struct otx2_cptlfs_info *lfs, u8 enable)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

186

for (slot = 0; slot < lfs->lfs_num; slot++)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

187

otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot, reg, 0x1);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

19

otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

194

irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

205

dev = &lf->lfs->pdev->dev;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

206

irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

239

otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

254

done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

257

otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

260

otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

263

dev_err(&lf->lfs->pdev->dev, "No work for LF %d\n",

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

27

done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

274

void otx2_cptlf_unregister_misc_interrupts(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

279

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

280

if (!lfs->lf[i].is_irq_reg[irq_offs])

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

283

vector = pci_irq_vector(lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

284

lfs->lf[i].msix_offset + irq_offs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

285

free_irq(vector, &lfs->lf[i]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

286

lfs->lf[i].is_irq_reg[irq_offs] = false;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

289

cptlf_set_misc_intrs(lfs, false);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

293

void otx2_cptlf_unregister_done_interrupts(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

298

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

299

if (!lfs->lf[i].is_irq_reg[irq_offs])

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

30

otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

302

vector = pci_irq_vector(lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

303

lfs->lf[i].msix_offset + irq_offs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

304

free_irq(vector, &lfs->lf[i]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

305

lfs->lf[i].is_irq_reg[irq_offs] = false;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

308

cptlf_set_done_intrs(lfs, false);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

312

static int cptlf_do_register_interrrupts(struct otx2_cptlfs_info *lfs,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

318

vector = pci_irq_vector(lfs->pdev, lfs->lf[lf_num].msix_offset +

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

321

lfs->lf[lf_num].irq_name[irq_offset],

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

322

&lfs->lf[lf_num]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

326

lfs->lf[lf_num].is_irq_reg[irq_offset] = true;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

331

int otx2_cptlf_register_misc_interrupts(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

333

bool is_cpt1 = (lfs->blkaddr == BLKADDR_CPT1);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

337

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

338

snprintf(lfs->lf[i].irq_name[irq_offs], 32, "CPT%dLF Misc%d",

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

34

static void cptlf_set_done_time_wait(struct otx2_cptlfs_info *lfs,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

340

ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

345

cptlf_set_misc_intrs(lfs, true);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

349

otx2_cptlf_unregister_misc_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

354

int otx2_cptlf_register_done_interrupts(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

356

bool is_cpt1 = (lfs->blkaddr == BLKADDR_CPT1);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

360

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

361

snprintf(lfs->lf[i].irq_name[irq_offs], 32,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

363

ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

368

cptlf_set_done_intrs(lfs, true);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

372

otx2_cptlf_unregister_done_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

377

void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

381

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

383

irq_set_affinity_hint(pci_irq_vector(lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

384

lfs->lf[slot].msix_offset +

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

386

free_cpumask_var(lfs->lf[slot].affinity_mask);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

39

for (slot = 0; slot < lfs->lfs_num; slot++)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

391

int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

393

struct otx2_cptlf_info *lf = lfs->lf;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

396

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

398

dev_err(&lfs->pdev->dev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

40

cptlf_do_set_done_time_wait(&lfs->lf[slot], time_wait);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

405

dev_to_node(&lfs->pdev->dev)),

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

409

ret = irq_set_affinity_hint(pci_irq_vector(lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

419

otx2_cptlf_free_irqs_affinity(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

424

int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

429

if (!lfs->pdev || !lfs->reg_base)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

43

static void cptlf_set_done_num_wait(struct otx2_cptlfs_info *lfs, int num_wait)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

432

lfs->lfs_num = lfs_num;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

433

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

434

lfs->lf[slot].lfs = lfs;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

435

lfs->lf[slot].slot = slot;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

436

if (!lfs->lmt_info.base)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

437

lfs->lf[slot].lmtline = lfs->reg_base +

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

441

lfs->lf[slot].ioreg = lfs->reg_base +

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

442

OTX2_CPT_RVU_FUNC_ADDR_S(lfs->blkaddr, slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

446

ret = otx2_cpt_attach_rscrs_msg(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

450

ret = otx2_cpt_alloc_instruction_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

452

dev_err(&lfs->pdev->dev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

456

cptlf_hw_init(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

461

ret = cptlf_set_grp_and_pri(lfs, eng_grp_mask, pri);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

465

if (lfs->ctx_ilen_ovrd) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

466

ret = cptlf_set_ctx_ilen(lfs, lfs->ctx_ilen);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

47

for (slot = 0; slot < lfs->lfs_num; slot++)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

474

cptlf_hw_cleanup(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

475

otx2_cpt_free_instruction_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

477

otx2_cpt_detach_rsrcs_msg(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

479

lfs->lfs_num = 0;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

48

cptlf_do_set_done_num_wait(&lfs->lf[slot], num_wait);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

484

void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

487

cptlf_hw_cleanup(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

489

otx2_cpt_free_instruction_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

491

otx2_cpt_detach_rsrcs_msg(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

492

lfs->lfs_num = 0;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

53

struct otx2_cptlfs_info *lfs = lf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

57

ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

59

&lf_ctrl.u, lfs->blkaddr);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

65

ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

67

lf_ctrl.u, lfs->blkaddr);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

74

struct otx2_cptlfs_info *lfs = lf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

78

ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

80

&lf_ctrl.u, lfs->blkaddr);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

86

ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

88

lf_ctrl.u, lfs->blkaddr);

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

92

static int cptlf_set_grp_and_pri(struct otx2_cptlfs_info *lfs,

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

97

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

98

ret = cptlf_set_pri(&lfs->lf[slot], pri);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

138

struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

143

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

144

iq = &lfs->lf[i].iqueue;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

146

dma_free_coherent(&lfs->pdev->dev,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

156

struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

161

if (!lfs->lfs_num)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

164

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

165

iq = &lfs->lf[i].iqueue;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

170

iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

187

otx2_cpt_free_instruction_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

192

struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

197

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

198

lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

199

otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

210

otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

214

static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

218

for (slot = 0; slot < lfs->lfs_num; slot++)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

219

otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

231

void __iomem *reg_base = lf->lfs->reg_base;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

232

struct pci_dev *pdev = lf->lfs->pdev;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

233

u8 blkaddr = lf->lfs->blkaddr;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

279

static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

283

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

284

otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

285

otx2_cpt_lf_reset_msg(lfs, lfs->global_slot + slot);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

292

u8 blkaddr = lf->lfs->blkaddr;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

295

lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

300

otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

313

u8 blkaddr = lf->lfs->blkaddr;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

315

lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

320

otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

326

u8 blkaddr = lf->lfs->blkaddr;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

329

val = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

333

otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

347

static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

351

for (slot = 0; slot < lfs->lfs_num; slot++) {

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

353

if (is_dev_cn10kb(lfs->pdev))

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

354

otx2_cptlf_set_ctx_flr_flush(&lfs->lf[slot]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

356

otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

357

otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

421

static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

423

return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

426

static inline void otx2_cptlf_set_dev_info(struct otx2_cptlfs_info *lfs,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

432

lfs->pdev = pdev;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

433

lfs->reg_base = reg_base;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

434

lfs->mbox = mbox;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

435

lfs->blkaddr = blkaddr;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

438

int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

440

void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

441

int otx2_cptlf_register_misc_interrupts(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

442

int otx2_cptlf_register_done_interrupts(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

443

void otx2_cptlf_unregister_misc_interrupts(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

444

void otx2_cptlf_unregister_done_interrupts(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

445

void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

446

int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

79

struct otx2_cptlfs_info *lfs;

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

84

struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

33

struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

75

struct otx2_cptlfs_info *lfs, u8 egrp, int num_lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

76

void otx2_inline_cptlf_cleanup(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

642

otx2_cptlf_set_dev_info(&cptpf->lfs, cptpf->pdev, cptpf->reg_base,

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

824

cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

845

if (cptpf->lfs.lfs_num)

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

846

otx2_inline_cptlf_cleanup(&cptpf->lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

860

cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

205

struct otx2_cptlfs_info *lfs, u8 egrp, int num_lfs)

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

209

ret = otx2_cptlf_init(lfs, 1 << egrp, OTX2_CPT_QUEUE_HI_PRIO, 1);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

217

ret = otx2_cpt_msix_offset_msg(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

222

ret = otx2_cptlf_register_misc_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

228

otx2_cptlf_unregister_misc_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

230

otx2_cptlf_shutdown(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

235

otx2_inline_cptlf_cleanup(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

238

otx2_cptlf_unregister_misc_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

241

otx2_cptlf_shutdown(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

252

if (cptpf->lfs.lfs_num) {

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

268

cptpf->lfs.global_slot = 0;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

269

cptpf->lfs.ctx_ilen_ovrd = cfg_req->ctx_ilen_valid;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

270

cptpf->lfs.ctx_ilen = cfg_req->ctx_ilen;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

272

ret = otx2_inline_cptlf_setup(cptpf, &cptpf->lfs, egrp, num_lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

301

otx2_inline_cptlf_cleanup(&cptpf->lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

452

struct otx2_cptlfs_info *lfs = &cptpf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

468

lfs = &cptpf->cpt1_lfs;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

477

lfs->lf[i].msix_offset = rsp_msix->cptlf_msixoff[i];

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

480

lfs->lf[i].msix_offset = rsp_msix->cpt1_lf_msixoff[i];

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

495

lfs->are_lfs_attached = 1;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

499

lfs->are_lfs_attached = 0;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

599

struct otx2_cptlfs_info *lfs = &cptpf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

602

if (cptpf->lfs.lfs_num)

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

603

lfs->ops->send_cmd((union otx2_cpt_inst_s *)req->inst, 1,

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

604

&lfs->lf[0]);

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1492

struct otx2_cptlfs_info *lfs = &cptpf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1521

ret = otx2_cptlf_init(lfs, OTX2_CPT_ALL_ENG_GRPS_MASK,

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1567

lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]);

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1570

while (lfs->ops->cpt_get_compcode(result) ==

drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

1592

otx2_cptlf_shutdown(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf.h

15

struct otx2_cptlfs_info lfs; /* CPT LFs attached to this VF */

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

133

static void cleanup_tasklet_work(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

137

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

138

if (!lfs->lf[i].wqe)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

141

tasklet_kill(&lfs->lf[i].wqe->work);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

142

kfree(lfs->lf[i].wqe);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

143

lfs->lf[i].wqe = NULL;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

147

static int init_tasklet_work(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

152

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

160

wqe->lfs = lfs;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

162

lfs->lf[i].wqe = wqe;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

167

cleanup_tasklet_work(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

171

static void free_pending_queues(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

175

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

176

kfree(lfs->lf[i].pqueue.head);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

177

lfs->lf[i].pqueue.head = NULL;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

181

static int alloc_pending_queues(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

185

if (!lfs->lfs_num)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

188

for (i = 0; i < lfs->lfs_num; i++) {

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

189

lfs->lf[i].pqueue.qlen = OTX2_CPT_INST_QLEN_MSGS;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

190

size = lfs->lf[i].pqueue.qlen *

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

193

lfs->lf[i].pqueue.head = kzalloc(size, GFP_KERNEL);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

194

if (!lfs->lf[i].pqueue.head) {

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

200

spin_lock_init(&lfs->lf[i].pqueue.lock);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

205

free_pending_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

209

static void lf_sw_cleanup(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

211

cleanup_tasklet_work(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

212

free_pending_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

215

static int lf_sw_init(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

219

ret = alloc_pending_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

221

dev_err(&lfs->pdev->dev,

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

225

ret = init_tasklet_work(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

227

dev_err(&lfs->pdev->dev,

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

234

free_pending_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

238

static void cptvf_lf_shutdown(struct otx2_cptlfs_info *lfs)

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

240

atomic_set(&lfs->state, OTX2_CPTLF_IN_RESET);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

243

otx2_cptlf_free_irqs_affinity(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

245

otx2_cptlf_disable_iqueues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

247

otx2_cpt_crypto_exit(lfs->pdev, THIS_MODULE);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

249

otx2_cptlf_unregister_misc_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

250

otx2_cptlf_unregister_done_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

252

lf_sw_cleanup(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

254

otx2_cpt_free_instruction_queues(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

256

otx2_cpt_detach_rsrcs_msg(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

257

lfs->lfs_num = 0;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

262

struct otx2_cptlfs_info *lfs = &cptvf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

268

cptvf->lfs.kcrypto_se_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

273

if (cptvf->lfs.kcrypto_se_eng_grp_num ==

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

281

cptvf->lfs.kcrypto_ae_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

286

if (cptvf->lfs.kcrypto_ae_eng_grp_num ==

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

293

eng_grp_msk = BIT(cptvf->lfs.kcrypto_se_eng_grp_num) |

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

294

BIT(cptvf->lfs.kcrypto_ae_eng_grp_num);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

300

lfs_num = cptvf->lfs.kvf_limits;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

302

ret = otx2_cptlf_init(lfs, eng_grp_msk, OTX2_CPT_QUEUE_HI_PRIO,

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

308

ret = otx2_cpt_msix_offset_msg(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

313

ret = lf_sw_init(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

318

ret = otx2_cptlf_register_misc_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

322

ret = otx2_cptlf_register_done_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

327

ret = otx2_cptlf_set_irqs_affinity(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

331

atomic_set(&lfs->state, OTX2_CPTLF_STARTED);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

333

ret = otx2_cpt_crypto_init(lfs->pdev, THIS_MODULE, lfs_num, 1);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

335

dev_err(&lfs->pdev->dev, "algorithms registration failed\n");

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

341

otx2_cptlf_free_irqs_affinity(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

343

otx2_cptlf_unregister_misc_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

344

otx2_cptlf_unregister_done_interrupts(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

346

lf_sw_cleanup(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

348

otx2_cptlf_shutdown(lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

409

otx2_cptlf_set_dev_info(&cptvf->lfs, cptvf->pdev, cptvf->reg_base,

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

418

cptvf->lfs.ops->cpt_sg_info_create = cn10k_sgv2_info_create;

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

432

cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

451

cptvf_lf_shutdown(&cptvf->lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c

457

cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

100

lfs->are_lfs_attached = 1;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

105

lfs->are_lfs_attached = 0;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

110

lfs->lf[i].msix_offset = rsp_msix->cptlf_msixoff[i];

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

128

cptvf->lfs.kcrypto_se_eng_grp_num = grp_num;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

130

cptvf->lfs.kcrypto_ae_eng_grp_num = grp_num;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

134

cptvf->lfs.kvf_limits = rsp_limits->kvf_limits;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

72

struct otx2_cptlfs_info *lfs = &cptvf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

101

if (unlikely(!otx2_cptlf_started(lf->lfs)))

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

104

info = lf->lfs->ops->cpt_sg_info_create(pdev, req, gfp);

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

177

lf->lfs->ops->send_cmd(&cptinst, 1, lf);

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

200

struct otx2_cptlfs_info *lfs = &cptvf->lfs;

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

202

return process_request(lfs->pdev, req, &lfs->lf[cpu_num].pqueue,

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

203

&lfs->lf[cpu_num]);

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

206

static int cpt_process_ccode(struct otx2_cptlfs_info *lfs,

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

211

u8 uc_ccode = lfs->ops->cpt_get_uc_compcode(cpt_status);

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

212

u8 ccode = lfs->ops->cpt_get_compcode(cpt_status);

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

213

struct pci_dev *pdev = lfs->pdev;

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

286

static inline void process_pending_queue(struct otx2_cptlfs_info *lfs,

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

296

struct pci_dev *pdev = lfs->pdev;

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

337

if (cpt_process_ccode(lfs, cpt_status, info, &res_code)) {

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

390

process_pending_queue(wqe->lfs,

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

391

&wqe->lfs->lf[wqe->lf_num].pqueue);

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

401

return cptvf->lfs.kcrypto_se_eng_grp_num;

drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

403

return cptvf->lfs.kcrypto_ae_eng_grp_num;

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

647

char *lfs)

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

665

len += sprintf(lfs + len, "-%d,%d", prev_lf, lf);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

667

len += (len ? sprintf(lfs + len, ",%d", lf) :

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

668

sprintf(lfs + len, "%d", lf));

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

675

len += sprintf(lfs + len, "-%d", prev_lf);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

677

lfs[len] = '\0';

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

725

char *lfs;

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

739

lfs = kzalloc(lf_str_size, GFP_KERNEL);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

740

if (!lfs) {

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

769

sprintf(lfs, "PF%d:VF%d", pf, vf - 1);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

772

"%-*s", lf_str_size, lfs);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

774

sprintf(lfs, "PF%d", pf);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

777

"%-*s", lf_str_size, lfs);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

785

lfs[len] = '\0';

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

786

get_lf_str_list(&block, pcifunc, lfs);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

787

if (strlen(lfs))

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

791

"%-*s", lf_str_size, lfs);

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

809

kfree(lfs);

fs/nfs/internal.h

356

dst->lfs = src->lfs;

fs/nfs/nfs4proc.c

125

label->lfs = 0;

fs/nfs/nfs4xdr.c

1190

*p++ = cpu_to_be32(label->lfs);

fs/nfs/nfs4xdr.c

4279

uint32_t lfs = 0;

fs/nfs/nfs4xdr.c

4290

lfs = be32_to_cpup(p++);

fs/nfs/nfs4xdr.c

4310

label->lfs = lfs;

fs/nfs/nfs4xdr.c

4319

label->len, label->pi, label->lfs);

fs/nfsd/nfs4xdr.c

358

u32 lfs, pi, length;

fs/nfsd/nfs4xdr.c

361

if (xdr_stream_decode_u32(argp->xdr, &lfs) < 0)

include/linux/nfs4.h

48

uint32_t lfs;

tools/testing/selftests/powerpc/alignment/alignment_handler.c

539

LOAD_FLOAT_DFORM_TEST(lfs);

tools/testing/selftests/powerpc/alignment/alignment_handler.c

597

LOAD_FLOAT_DFORM_TEST(lfs);