kmb_write_mipi
kmb_write_mipi(kmb_dsi,
kmb_write_mipi(kmb_dsi, reg_adr, height_lines);
kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->v_active);
kmb_write_mipi(kmb_dsi, reg_adr,
kmb_write_mipi(kmb_dsi, reg_adr,
kmb_write_mipi(kmb_dsi, reg_adr,
kmb_write_mipi(kmb_dsi, reg_adr, val);
kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8));
kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8));
kmb_write_mipi(kmb_dsi, reg_adr,
kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_CTRL_EN, 0);
kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0);
kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0);
kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0);
kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0);
kmb_write_mipi(kmb_dsi, MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg);
kmb_write_mipi(kmb_dsi, MIPI_TXm_HS_CTRL(ctrl_no), ctrl);
kmb_write_mipi(kmb_dsi,
kmb_write_mipi(kmb_dsi, reg, reg_val);
kmb_write_mipi(kmb_dsi, reg, reg_val | (1 << offset));
kmb_write_mipi(kmb_dsi, reg, reg_val & (~(1 << offset)));
kmb_write_mipi(dev, DPHY_TEST_DIN0_3 + \