drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

264

pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

265

pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

266

pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

284

pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

285

pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

286

pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

135

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

268

pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

275

pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

281

pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.socclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

296

pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

321

pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.disp_dpp_voltage_level_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

516

pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

153

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

162

ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

177

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

192

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

202

khz_to_mhz_ceil(requested_phyclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

212

khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

214

ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

240

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

245

dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

290

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

297

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

303

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

372

(uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

491

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

155

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

169

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

185

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

199

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

213

khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

167

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

182

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

202

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

220

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

235

khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

186

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

201

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

221

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

239

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

254

khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

197

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

215

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

233

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

248

khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

172

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

190

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

208

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

223

khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1021

(uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

239

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

241

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

250

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

252

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

698

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

704

dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

774

khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

776

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

822

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

204

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

220

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

237

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

254

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

271

khz_to_mhz_ceil(requested_dpp_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1133

block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

294

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

296

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

302

< (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

304

= (unsigned int)khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

611

actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_ceil(requested_clk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

792

int active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

793

int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

794

int idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

795

int idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

796

int subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_dramclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

797

int subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_fclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

856

block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

867

block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

943

active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

952

idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

959

subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_dramclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

969

active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

978

idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

985

subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_fclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

192

khz_to_mhz_ceil(requested_dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

210

khz_to_mhz_ceil(requested_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

228

khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

246

khz_to_mhz_ceil(requested_dpp_khz));