drivers/gpu/drm/amd/display/dc/dc_dp_types.h

517

union lane_status lane01_status;/* 202h */

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

518

union lane_status lane23_status;/* 203h */

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1180

union lane_status *status,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1213

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

54

union lane_status lane_status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

72

lane_status.raw = dp_get_nibble_at_index(

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

76

if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

77

!lane_status.bits.CR_DONE_0 ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

78

!lane_status.bits.SYMBOL_LOCKED_0) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1432

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

442

union lane_status *dpcd_lane_status)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

478

union lane_status *dpcd_lane_status)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

492

union lane_status *dpcd_lane_status)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

503

union lane_status *dpcd_lane_status)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

558

union lane_status lane_status;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

574

lane_status.raw = dp_get_nibble_at_index(&dpcd_buf[2], lane);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

577

if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

578

!lane_status.bits.CR_DONE_0 ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

579

!lane_status.bits.SYMBOL_LOCKED_0 ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

597

union lane_status ln_status[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

141

union lane_status *dpcd_lane_status);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

144

union lane_status *dpcd_lane_status);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

146

union lane_status *dpcd_lane_status);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

157

union lane_status *dpcd_lane_status);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

83

union lane_status ln_status[LANE_COUNT_DP_MAX],

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

165

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

80

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

231

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

352

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

300

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

466

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

596

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

740

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

327

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

457

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

307

u8 lane_status;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

310

lane_status = analogix_dp_get_lane_status(link_status, lane);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

311

if ((lane_status & DP_LANE_CR_DONE) == 0)

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

321

u8 lane_status;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

327

lane_status = analogix_dp_get_lane_status(link_status, lane);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

328

lane_status &= DP_CHANNEL_EQ_BITS;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

329

if (lane_status != DP_CHANNEL_EQ_BITS)

drivers/gpu/drm/display/drm_dp_helper.c

104

lane_status = dp_get_lane_status(link_status, lane);

drivers/gpu/drm/display/drm_dp_helper.c

105

if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)

drivers/gpu/drm/display/drm_dp_helper.c

116

u8 lane_status;

drivers/gpu/drm/display/drm_dp_helper.c

119

lane_status = dp_get_lane_status(link_status, lane);

drivers/gpu/drm/display/drm_dp_helper.c

120

if ((lane_status & DP_LANE_CR_DONE) == 0)

drivers/gpu/drm/display/drm_dp_helper.c

179

u8 lane_align, lane_status;

drivers/gpu/drm/display/drm_dp_helper.c

187

lane_status = dp_get_lane_status(link_status, lane);

drivers/gpu/drm/display/drm_dp_helper.c

188

if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))

drivers/gpu/drm/display/drm_dp_helper.c

199

u8 lane_status;

drivers/gpu/drm/display/drm_dp_helper.c

203

lane_status = dp_get_lane_status(link_status, lane);

drivers/gpu/drm/display/drm_dp_helper.c

204

if (!(lane_status & DP_LANE_SYMBOL_LOCKED))

drivers/gpu/drm/display/drm_dp_helper.c

96

u8 lane_status;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1317

uint8_t lane_status;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1320

lane_status = cdv_intel_get_lane_status(link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1321

if ((lane_status & DP_LANE_CR_DONE) == 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1336

uint8_t lane_status;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1344

lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1345

if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

139

u8 lane_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

145

train_set[lane] = drm_dp_get_adjust_request_voltage(lane_status, lane) |

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

146

drm_dp_get_adjust_request_pre_emphasis(lane_status, lane);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

200

u8 lane_status[DP_LINK_STATUS_SIZE] = {0};

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

215

ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

221

if (drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) {

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

233

level_changed = hibmc_dp_link_get_adjust_train(dp, lane_status);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

257

u8 lane_status[DP_LINK_STATUS_SIZE] = {0};

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

268

ret = drm_dp_dpcd_read_link_status(dp->aux, lane_status);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

274

if (!drm_dp_clock_recovery_ok(lane_status, dp->link.cap.lanes)) {

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

281

if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) {

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

287

hibmc_dp_link_get_adjust_train(dp, lane_status);

drivers/net/ethernet/sfc/falcon/mdio_10g.h

42

int i, lane_status;

drivers/net/ethernet/sfc/falcon/mdio_10g.h

46

lane_status = ef4_mdio_read(efx, MDIO_MMD_PHYXS,

drivers/net/ethernet/sfc/falcon/mdio_10g.h

49

sync = !!(lane_status & MDIO_PHYXS_LNSTAT_ALIGN);

drivers/net/ethernet/sfc/falcon/mdio_10g.h

52

lane_status);