A23
ASPEED_PINCTRL_PIN(A23),
{ PIN_CONFIG_DRIVE_STRENGTH, { D22, A23 }, SCU458, GENMASK(9, 8)},
SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15));
SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15));
PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15);
GROUP_DECL(PWM15G0, A23);
FUNC_GROUP_DECL(SD1, D22, E22, D23, C23, C22, A25, A24, A23);
PINMUX_IPSR_GPSR(IP7_3_0, A23),
PINMUX_IPSR_GPSR(IP1_7_5, A23),
PINMUX_IPSR_GPSR(IP0_15_14, A23),
PINMUX_IPSR_GPSR(IP4_8_6, A23),
PINMUX_IPSR_GPSR(IP2_12_10, A23),
PINMUX_IPSR_GPSR(IP1_20, A23),
PINMUX_IPSR_GPSR(IP3_5_4, A23),
#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2SR1_31_28, A23),
GPIO_FN(A23),
GPIO_FN(A23),
GPIO_FN(A23),
GPIO_FN(A23),
GPIO_FN(A23),
A23, PTE5_OUT, 0, PTE5_IN,
PINMUX_DATA(A23_MARK, A23),
GPIO_FN(A23),
GPIO_FN(A23),
GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
PINMUX_IPSR_GPSR(IP1_15_14, A23),
GPIO_FN(A23),