ADDR_SURF_BANK_WIDTH_4
macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |