l64781_writereg
l64781_writereg (state, 0x04, val0x04);
l64781_writereg (state, 0x05, val0x05);
l64781_writereg (state, 0x06, val0x06);
l64781_writereg (state, 0x15,
l64781_writereg (state, 0x16, init_freq & 0xff);
l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
l64781_writereg (state, 0x1b, spi_bias & 0xff);
l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
return l64781_writereg (state, 0x3e, 0x5a);
l64781_writereg (state, 0x3e, 0xa5);
l64781_writereg (state, 0x2a, 0x04);
l64781_writereg (state, 0x2a, 0x00);
l64781_writereg (state, 0x07, 0x8e);
l64781_writereg (state, 0x0b, 0x81);
l64781_writereg (state, 0x0c, 0x84);
l64781_writereg (state, 0x0d, 0x8c);
l64781_writereg (state, 0x1e, 0x09);
l64781_writereg (state, 0x3e, 0x5a);
l64781_writereg (state, 0x3e, 0xa5);
l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */
l64781_writereg (state, 0x2a, 0x00);
l64781_writereg (state, 0x2a, 0x01);
l64781_writereg (state, 0x2a, 0x02);
l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */
l64781_writereg (state, 0x09, 0);
l64781_writereg (state, 0x0a, 0);
l64781_writereg (state, 0x07, 0x8e);
l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */
l64781_writereg (state, 0x11, 0x80); /* stall TIM */
l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */
l64781_writereg (state, 0x12, 0);
l64781_writereg (state, 0x13, 0);
l64781_writereg (state, 0x11, 0x00);